Patent US5926053A successfully refreshed from Google Patents.
US5926053A
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US
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Selectable clock generation mode
Assignee: VIA Cyrix Inc
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Filing: 1995-12-15
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Granted: 1999-07-20
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Expires: 2015-12-15
Abstract
Abstract A processing system includes circuitry and methodology for selecting clock generation modes between phase-locked loop and static delay line loop circuitries. The node may be selectable through an externally accessible pin, an internal bond wire option, a boundary test scan control point, or other programmable register or control point.
Inventors
- 👤 Mark W. McDermott
- 👤 Antone L. Fourcroy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:25
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/322; G06F9/325; G06F1/00; G06F1/04; G06F1/10; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3228; G06F1/3234; G06F1/3237; G06F1/324; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
58 words
Clock generation circuitry comprising: (a) phase-locked loop circuitry; (b) delay line loop clock generator circuitry; and, (c) multiplexer circuitry having a first input coupled to the phase-locked loop circuitry, a second input coupled to the delay line loop clock generator circuitry, an output, and a third input to steer either the first or second input to the output.
Claim 2
Dependent Claim
58 words
Clock generation circuitry comprising: (a) phase-locked loop circuitry; (b) delay line loop clock generator circuitry; and, (c) multiplexer circuitry having a first input coupled to the phase-locked loop circuitry, a second input coupled to the delay line loop clock generator circuitry, an output, and a third input to steer either the first or second input to the output.
Claim 3
Dependent Claim
58 words
Clock generation circuitry as recited in claim 1 wherein the phase-locked loop circuitry includes an in-lock output to indicate within lock range and wherein the in-lock output is coupled to the third input to steer the phase-locked loop circuitry to the output when within lock range, otherwise steering the delay line loop clock generator circuitry to the output.
Claim 4
Dependent Claim
27 words
Clock generation circuitry as recited in claim 1 wherein the third input is internally hardwired with a bond wire to either a logic high or low value.
Claim 5
Dependent Claim
19 words
Clock generation circuitry as recited in claim 1 wherein the third input is bonded-out to an externally accessible pin.
Claim 6
Dependent Claim
32 words
Clock generation circuitry as recited in claim 1 further comprising boundary scan test logic circuitry wherein the third input is coupled to a control point within the boundary scan test logic circuitry.
Claim 7
Dependent Claim
31 words
Clock generation circuitry as recited in claim 1 wherein the phase-locked loop circuitry and the delay line loop clock generator circuitry further include an enable input coupled to the third input.
Claim 8
Dependent Claim
64 words
Clock generation circuitry comprising: (a) means for generating a phase-locked loop clock signal based upon an applied external clock signal; (b) means for generating a delay line loop clock signal based upon an initiating edge of the applied external clock signal; and, (c) multiplexer means for steering either the phase-locked loop clock signal or the delay line loop clock signal as a clock source.
Claim 9
Dependent Claim
64 words
Clock generation circuitry comprising: (a) means for generating a phase-locked loop clock signal based upon an applied external clock signal; (b) means for generating a delay line loop clock signal based upon an initiating edge of the applied external clock signal; and, (c) multiplexer means for steering either the phase-locked loop clock signal or the delay line loop clock signal as a clock source.
Claim 10
Dependent Claim
58 words
Clock generation circuitry as recited in claim 7 wherein the means for generating a phase-locked loop clock signal further includes means for indicating within lock range, coupled to the multiplexer means, to steer the phase-locked loop clock signal as the clock source when within lock range, otherwise steering the delay line loop clock signal as the clock source.
Claim 11
Dependent Claim
24 words
Clock generation circuitry as recited in claim 7 further comprising boundary scan test means for generating a control point to control the multiplexer means.
Claim 12
Dependent Claim
35 words
Clock generation circuitry as recited in claim 7 further comprising enabling means for enabling either the means for generating a phase-locked loop clock signal or the means for generating a delay line loop clock signal.
Claim 13
Independent Claim
70 words
A method of generating a clock source comprising steps of: (a) receiving an applied external clock signal; (b) generating a phase-locked loop clock signal based upon the applied external clock signal; (c) generating a delay line loop clock signal based upon an initiating edge of the applied external clock signal; and, (d) steering either the phase-locked loop clock signal or the delay line loop clock signal as a clock source.
Claim 14
Independent Claim
70 words
A method of generating a clock source comprising steps of: (a) receiving an applied external clock signal; (b) generating a phase-locked loop clock signal based upon the applied external clock signal; (c) generating a delay line loop clock signal based upon an initiating edge of the applied external clock signal; and, (d) steering either the phase-locked loop clock signal or the delay line loop clock signal as a clock source.
Claim 15
Dependent Claim
50 words
A method as recited in claim 11 further comprising steps of: (e) indicating within lock range for the phase-locked loop clock signal; and, (f) steering the phase-locked loop clock signal as the clock source when within lock range, otherwise steering the delay line loop clock signal as the clock source.
Claim 16
Dependent Claim
85 words
A computer system comprising: (a) a motherboard; (b) memory disposed on the motherboard; and, (c) a processor disposed on the motherboard coupled to the memory and including clock generation circuitry having, (i) phase-locked loop circuitry; (ii) delay line loop clock generator circuitry; and, (iii) multiplexer circuitry having a first input coupled to the phase-locked loop circuitry, a second input coupled to the delay line loop clock generator circuitry, an output, and a third input to steer either the first or second input to the output.
Claim 17
Dependent Claim
85 words
A computer system comprising: (a) a motherboard; (b) memory disposed on the motherboard; and, (c) a processor disposed on the motherboard coupled to the memory and including clock generation circuitry having, (i) phase-locked loop circuitry; (ii) delay line loop clock generator circuitry; and, (iii) multiplexer circuitry having a first input coupled to the phase-locked loop circuitry, a second input coupled to the delay line loop clock generator circuitry, an output, and a third input to steer either the first or second input to the output.
Claim 18
Dependent Claim
102 words
In a computer having a motherboard, a processor, and system memory external to the processor, a method of a clock generation comprising steps of: (a) receiving an applied external clock signal; (b) generating a phase-locked loop clock signal based upon the applied external clock signal; (c) generating a delay line loop clock signal based upon an initiating edge of the applied external clock signal; (d) steering either the phase-locked loop clock signal or the delay line loop clock signal as a clock source; (e) retrieving instructions from system memory; and, (f) executing the instructions with the processor synchronous with the clock source.
Claim 19
Dependent Claim
102 words
In a computer having a motherboard, a processor, and system memory external to the processor, a method of a clock generation comprising steps of: (a) receiving an applied external clock signal; (b) generating a phase-locked loop clock signal based upon the applied external clock signal; (c) generating a delay line loop clock signal based upon an initiating edge of the applied external clock signal; (d) steering either the phase-locked loop clock signal or the delay line loop clock signal as a clock source; (e) retrieving instructions from system memory; and, (f) executing the instructions with the processor synchronous with the clock source.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-19 | 2003-01-18 | 2003-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-19 | 2007-01-18 | 2007-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-19 | 2011-01-18 | 2011-07-20 | $7700.00 | Window Closed / Lapsed |