US4933955A
Expired / Lapsed
US
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Timing generator
Assignee: Silicon General Inc
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Filing: 1988-02-26
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Granted: 1990-06-12
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Expires: 2008-02-26
Abstract
Abstract The circuitry of the present invention taps a DS0 data stream and outputs a timing signal to drive terminal multiplexers. Even if the data bit stream is lost, the present invention continues to provide proper clocking signals. A composite clock (bit and byte clock) is provided by the present invention with the bit clock at 64 KHz and the byte clock at 8 KHz in the preferred embodiment. To avoid the problem of phase shift over long distances (limiting cable length) the present invention phase adjusts the digital bit stream clocking signal with a 360 degree delay, giving the appearance of advancing the signal in phase. An additional delay of one frame width is applied to the signal. A negative phase delay equivalent to cable runs from 0-1500 feet in 500 foot increments is also applied. In the preferred embodiment, a shift register is tapped in reverse order to accomplish this phase delay.
Inventors
- 👤 Toney Warren
- 👤 Steven Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:19
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0635; H04J3/0685; H04J3/0688; H04L; H04L7/00; H04L7/0016; H04L7/0033; H04L7/0037
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
141 words
A timing circuit comprising: first clock input means for receiving first and second clock input signals, said first clock input signal having frequency information and said second clock input signal having frequency and phase information, said first clock input means selecting one of said first and second clock input signals and providing a first output signal; first timing output means coupled to said first output signal, said first timing output means for providing a second output signal having frequency and phase information when said first clock input signal is selected; second timing outpout means coupled to said first output signal, said second timing output means for providing a third output signal having frequency information when said second clock input signal is selected; said first timing output means having phase delay means for introducing a phase delay into said first output signal.
Claim 2
Dependent Claim
141 words
A timing circuit comprising: first clock input means for receiving first and second clock input signals, said first clock input signal having frequency information and said second clock input signal having frequency and phase information, said first clock input means selecting one of said first and second clock input signals and providing a first output signal; first timing output means coupled to said first output signal, said first timing output means for providing a second output signal having frequency and phase information when said first clock input signal is selected; second timing outpout means coupled to said first output signal, said second timing output means for providing a third output signal having frequency information when said second clock input signal is selected; said first timing output means having phase delay means for introducing a phase delay into said first output signal.
Claim 3
Dependent Claim
28 words
The circuit of claim 1 wherein said first clock input means comprises first and second phase locking means coupled to said first and second clock input signals respectively.
Claim 4
Dependent Claim
16 words
The circuit of claim 1 wherein said first clock input signal comprises a composite clock signal.
Claim 5
Dependent Claim
18 words
The circuit of claim 3 wherein said composite clock signal comprises an alternate mark inversion format clock signal.
Claim 6
Dependent Claim
17 words
The circuit of claim 1 wherein said second clock input signal comprises a DS1 format clock signal.
Claim 7
Dependent Claim
50 words
The circuit of claim 1 wherein said phase delay means comprises a shift register having a plurality of selectable taps, each of said taps providing a predetermined phase delay to said first output signal and further including swtiching means coupled to said shift register for selecting one of said taps.
Claim 8
Dependent Claim
48 words
The circuit of claim 1 further including second clock input means for receiving said first and second clock signals, said second clock input means selecting one of said first and second clock input signals and providing a fourth output signal to said first and second timing output means.
Claim 9
Dependent Claim
173 words
A timing circuit comprising: first and second clock input means for receiving first and second clock input signals, said first and second clock input means for selecting one of said first and second clock input signals and providing first and second output signals respectively; first timing output means coupled to said first and second output signals for selecting one of said first and second output signal and providing a third output signal having frequency and phase information when said first clock input signal is selected; second timing output means coupled to said first and second output signals for selecting one of said first and second output signals and providing a fourth output signal having frequency information when said second clock input signal is selected; said first clock input signal comprising a composite clock signal having frequency information; said second clock input signal comprising a DS1 clock signal having phase and frequency information; said first timing output means having phase delay means for introducing a phase delay to said first and second output signals.
Claim 10
Dependent Claim
173 words
A timing circuit comprising: first and second clock input means for receiving first and second clock input signals, said first and second clock input means for selecting one of said first and second clock input signals and providing first and second output signals respectively; first timing output means coupled to said first and second output signals for selecting one of said first and second output signal and providing a third output signal having frequency and phase information when said first clock input signal is selected; second timing output means coupled to said first and second output signals for selecting one of said first and second output signals and providing a fourth output signal having frequency information when said second clock input signal is selected; said first clock input signal comprising a composite clock signal having frequency information; said second clock input signal comprising a DS1 clock signal having phase and frequency information; said first timing output means having phase delay means for introducing a phase delay to said first and second output signals.
Claim 11
Dependent Claim
18 words
The circuit of claim 8 wherein said composite clock signal comprises an alternate mark inversion format clock signal.
Claim 12
Dependent Claim
66 words
The circuit of claim 8 wherein said phase delay means comprises a shift register coupled to a selected one of said first and second output signals and having a plurality of taps, each of said taps providing a predetermined phase delay to said selected signal, said phase delay means further including switching means coupled to said shift register for selecting one of said plurality of taps.
Claim 13
Dependent Claim
45 words
The circuit of claim 10 wherein said plurality of taps comprises first second third and fourth taps, said fourth tap introducing a phase delay of 360° and each preceding tap introducing a delay of one clock period of said first and second clock input signals.
Claim 14
Dependent Claim
26 words
The circuit of claim 8 wherein said first and second timing output means include switching means for selecting one of said first and second output signals.
Claim 15
Dependent Claim
25 words
The circuit of claim 8 wherein said second clock input means includes decoding means for decoding phase information contained in said second clock input signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-11 | 1993-12-11 | 1994-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-11 | 1997-12-11 | 1998-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-11 | 2001-12-11 | 2002-06-12 | $7700.00 | Window Closed / Lapsed |