US4630291A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Externally synchronized timebase
Assignee: Alcatel CIT SA
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Filing: 1984-05-25
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Granted: 1986-12-16
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Expires: 2004-05-25
Abstract
Abstract A timebase adapted to be synchronized to an external clock comprises at least one generator incorporating a voltage-controlled oscillator adapted to be controlled by the result of comparing an external synchronization signal from an external clock with an output signal of the timebase. Each generator comprises at least one differential comparator receiving the external synchronization signal and the timebase output signal. It drives a summing circuit on the input side of the control input of the oscillator of the generator in question. The generator further comprises a calibration system comprising a threshold detector connected to the output of the phase comparator, a calibration voltage adjustment circuit connected between the threshold detector and a second input of the summing circuit, and a trigger circuit in and controlling the adjustment circuit.
Inventors
- 👤 Andre Lankar
- 👤 Alain Lalanne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 05:48
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0635; H04J3/0676; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/14; H04J3/0685; H04J3/0691
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
279 words
A multi-generator externally synchronized timebase including a plurality of generators each generating first clock signals and individual output synchronization signals, each generator in said timebase comprising: a voltage-controlled oscillator (OS) for generating a first clock signal (HA) in accordance with a control input; a first voter (SM1) for deriving a majority clock signal from the individual first clock signals (Hij) respectively generated in each generator of said timebase; a second voter (SM2) for deriving an output synchronization signal (SL) from the individual output synchronization signals (Sij) respectively generated in each generator of said timebase; a first differential phase comparator (CP2) having a first input for receiving an external synchronization signal (Sk0) and a second input for receiving the derived output synchronization signal (SL); a second differential phase comparator (CP1) having a first input for receiving said derived majority clock signal and a second input for receiving an output signal (HA or HB) from said voltage controlled oscillator; a calibration circuit including a threshold detector (DS1) connected to an output of said first differential phase comparator (CP2), a first trigger circuit (CDE) responsive to said derived output synchronization signal (SL) and to outputs of said threshold detector for providing trigger circuit outputs, and a calibration voltage adjustment circuit (CRT) receiving said trigger circuit outputs and providing a calibration voltage adjustment circuit output; and a summing circuit (SS) having a first input receiving said calibration voltage adjustment circuit output, a second input receiving an output of said first differential phase comparator circuit and a third input receiving an output of said second differential phase comparator circuit, said summing circuit providing an output to said control input of said voltage controlled oscillator.
Claim 2
Dependent Claim
279 words
A multi-generator externally synchronized timebase including a plurality of generators each generating first clock signals and individual output synchronization signals, each generator in said timebase comprising: a voltage-controlled oscillator (OS) for generating a first clock signal (HA) in accordance with a control input; a first voter (SM1) for deriving a majority clock signal from the individual first clock signals (Hij) respectively generated in each generator of said timebase; a second voter (SM2) for deriving an output synchronization signal (SL) from the individual output synchronization signals (Sij) respectively generated in each generator of said timebase; a first differential phase comparator (CP2) having a first input for receiving an external synchronization signal (Sk0) and a second input for receiving the derived output synchronization signal (SL); a second differential phase comparator (CP1) having a first input for receiving said derived majority clock signal and a second input for receiving an output signal (HA or HB) from said voltage controlled oscillator; a calibration circuit including a threshold detector (DS1) connected to an output of said first differential phase comparator (CP2), a first trigger circuit (CDE) responsive to said derived output synchronization signal (SL) and to outputs of said threshold detector for providing trigger circuit outputs, and a calibration voltage adjustment circuit (CRT) receiving said trigger circuit outputs and providing a calibration voltage adjustment circuit output; and a summing circuit (SS) having a first input receiving said calibration voltage adjustment circuit output, a second input receiving an output of said first differential phase comparator circuit and a third input receiving an output of said second differential phase comparator circuit, said summing circuit providing an output to said control input of said voltage controlled oscillator.
Claim 3
Dependent Claim
74 words
A timebase according to claim 1, further comprising a programmable counter operating as a divider and having a clock input connected to said voltage-controlled oscillator and an output delivering the timebase output signal to said first phase comparator which is also connected to receive said external synchronization signal, whereby in the event that a predetermined phase difference threshold is exceeded said counter is restarted from a programmed value which yields a null phase difference.
Claim 4
Dependent Claim
211 words
A timebase according to claim 2, comprising a link supplying said external synchronization signal, a signaling link adapted to indicate characteristic states of said external synchronization signal and supplying said external synchronization signal and a group of monostables, said first trigger circuit including an adjustment pulse trigger monostable and two control gates connected between the outputs of said threshold detector and the inputs of said first counter, the output of said adjustment pulse trigger monostable being connected to the inputs of said control gates, and wherein said generator further comprises: a further comparator (CP3) having inputs connected to receive the output signal of said programmable counter and said external synchronization signal and an output adapted to produce a signal for a phase difference exceeding a threshold which is higher than that of said threshold detector, a second trigger circuit (TS) having an input connected to said further comparator and having a further input connected to the output of a monostable of said group via an OR gate and a time-delay monostable (MR2), and an adjustment pulse transmission period select counter (CR3) having an output connected to the input of said adjustment pulse trigger monostable in parallel with said second trigger circuit (TS) via a set of logic gates (P6 to P8).
Claim 5
Dependent Claim
119 words
A timebase according to claim 1, wherein: said calibration voltage adjustment circuit comprises a counter having incrementing and decrementing inputs each receiving a trigger circuit output, and a digital-to-analog converter having inputs selectively connected to outputs of said counter wherein said digital-to-analog converter has an output connected to said first input of said summing circuit, to permit temporary storage of said calibration voltage, and said first trigger circuit comprises a divider connected to receive at least one signal derived from the output of said voltage controlled oscillator, two control gates connected between the outputs of said threshold detector and the inputs of said counter, and a monostable connected to an output of said divider and controlling said control gates.
Claim 6
Dependent Claim
83 words
A timebase according to claim 1, comprising a threshold control circuit connected to the output of said first differential phase comparator and adapted to control the input of said calibration voltage adjustment circuit, said threshold control circuit being adapted to inhibit the input of said calibration voltage adjustment circuit when the phase difference threshold exceeds a predetermined value which is higher than the threshold of said detector, whereby external synchronization is inhibited if said signal is affected by drift exceeding a fixed value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-15 | 1990-06-16 | 1990-12-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-15 | 1994-06-16 | 1994-12-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-15 | 1998-06-16 | 1998-12-16 | $7700.00 | Window Closed / Lapsed |