Patent US5925918A successfully refreshed from Google Patents.
US5925918A
Expired / Lapsed
US
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Gate stack with improved sidewall integrity
Assignee: Round Rock Research LLC
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Filing: 1997-07-30
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Granted: 1999-07-20
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Expires: 2017-07-30
Abstract
Abstract A process of manufacturing a gate stack is disclosed whereby the integrity of both the gate sidewalls and the substrate surface is maintained. Nitride spacers are constructed on the sidewalls of a gate which has been etched only to the top of the polysilicon layer. This allows more of the polysilicon sidewall to be exposed during subsequent reoxidation while at the same time minimizing effects such as bird's beak resulting during reoxidation. After the nitride spacers are constructed the subsequent etch is performed in two steps in order to minimize degradation of the substrate surface in underlying active regions.
Inventors
- 👤 Zhiqiang Wu
- 👤 Pai-Hung Pan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:15
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01312; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/664; H10D64/671; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/267; H10P50/268; Y; Y10; Y10S; Y10S257/00; Y10S257/90; Y10S257/915
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
112 words
A semiconductor device comprising a plurality of gates on a gate oxide layer which has been grown on a silicon substrate, each of the plurality of gates comprising: a polysilicon layer adjacent to the gate oxide layer; a conductive layer adjacent to the polysilicon layer, wherein the conductive layer comprises a metal layer, and a metal nitride layer interposed between the metal layer and the polysilicon layer; sidewalls exposing the conductive layer and some portion of the polysilicon layer; and a first oxidation barrier on each of the gates' sidewalls, wherein the oxidation barrier covers the exposed sidewall of the conductive layer and a portion of the exposed sidewall of the polysilicon.
Claim 2
Dependent Claim
112 words
A semiconductor device comprising a plurality of gates on a gate oxide layer which has been grown on a silicon substrate, each of the plurality of gates comprising: a polysilicon layer adjacent to the gate oxide layer; a conductive layer adjacent to the polysilicon layer, wherein the conductive layer comprises a metal layer, and a metal nitride layer interposed between the metal layer and the polysilicon layer; sidewalls exposing the conductive layer and some portion of the polysilicon layer; and a first oxidation barrier on each of the gates' sidewalls, wherein the oxidation barrier covers the exposed sidewall of the conductive layer and a portion of the exposed sidewall of the polysilicon.
Claim 3
Dependent Claim
13 words
The semiconductor device of claim 1, wherein the first oxidation barrier comprises nitride.
Claim 4
Dependent Claim
19 words
The semiconductor of claim 1, further comprising a second oxidation barrier covering the entire surface of the gates' sidewalls.
Claim 5
Dependent Claim
13 words
The semiconductor device of claim 3, wherein the second oxidation barrier comprises nitride.
Claim 6
Dependent Claim
111 words
A semiconductor device comprising a plurality of gates on a gate oxide layer which has been grown on a silicon substrate, each of the plurality of gates comprising: a polysilicon layer adjacent to the gate oxide layer; a conductive layer adjacent to the polysilicon layers wherein the conductive layer comprises a metal layer, and a metal nitride layer interposed between the metal layer and the polysilicon layer; sidewalls exposing the conductive layer and some portion of the polysilicon layer; and a nitride spacer on each of the gates' sidewalls, wherein the nitride spacer covers the exposed sidewall of the conductive layer and a portion of the exposed sidewall of the polysilicon.
Claim 7
Dependent Claim
111 words
A semiconductor device comprising a plurality of gates on a gate oxide layer which has been grown on a silicon substrate, each of the plurality of gates comprising: a polysilicon layer adjacent to the gate oxide layer; a conductive layer adjacent to the polysilicon layers wherein the conductive layer comprises a metal layer, and a metal nitride layer interposed between the metal layer and the polysilicon layer; sidewalls exposing the conductive layer and some portion of the polysilicon layer; and a nitride spacer on each of the gates' sidewalls, wherein the nitride spacer covers the exposed sidewall of the conductive layer and a portion of the exposed sidewall of the polysilicon.
Claim 8
Dependent Claim
15 words
The semiconductor device of claim 5, further comprising a second spacer covering the gates' sidewalls.
Claim 9
Dependent Claim
12 words
The semiconductor device of claim 6, wherein the second spacer comprises nitride.
Claim 10
Dependent Claim
127 words
A semiconductor device comprising a plurality of gates on a gate oxide layer which has been grown on a silicon substrate, each of the plurality of gates comprising: a polysilicon layer adjacent to the gate oxide layer; a conductive layer adjacent to the polysilicon layer, wherein the conductive layer comprises layers of titanium nitride, tungsten and nitride; sidewalls exposing the conductive layer and some portion of the polysilicon layer; and a first oxidation barrier on each of the gates' sidewalls, wherein the oxidation barrier comprises nitride spacers; each of the gates having sidewalls exposing the conductive layer and some part of the polysilicon layer, wherein the first oxidation barrier covers the exposed sidewall of the conductive layer and a portion of the exposed sidewall of the polysilicon.
Claim 11
Dependent Claim
127 words
A semiconductor device comprising a plurality of gates on a gate oxide layer which has been grown on a silicon substrate, each of the plurality of gates comprising: a polysilicon layer adjacent to the gate oxide layer; a conductive layer adjacent to the polysilicon layer, wherein the conductive layer comprises layers of titanium nitride, tungsten and nitride; sidewalls exposing the conductive layer and some portion of the polysilicon layer; and a first oxidation barrier on each of the gates' sidewalls, wherein the oxidation barrier comprises nitride spacers; each of the gates having sidewalls exposing the conductive layer and some part of the polysilicon layer, wherein the first oxidation barrier covers the exposed sidewall of the conductive layer and a portion of the exposed sidewall of the polysilicon.
Claim 12
Dependent Claim
27 words
The semiconductor device of claim 8, further comprising a second oxidation barrier covering the entire surface of the gates' sidewalls, wherein the second oxidation barrier comprises nitride.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-07-19 | 2003-01-18 | 2003-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-19 | 2007-01-18 | 2007-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-19 | 2011-01-18 | 2011-07-20 | $7700.00 | Window Closed / Lapsed |