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US5459345A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device high dielectric capacitor with narrow contact hole

Assignee: Mitsubishi Electric Corp
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Filing: 1994-06-22
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Granted: 1995-10-17
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Expires: 2014-06-22
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Abstract

Abstract An object of the invention is to provide a semiconductor device which has a capacitor having good anti-leak characteristics and good breakdown voltage characteristics and is suitable to high integration. Source/drain regions (25) are formed at a surface of a silicon substrate (31). Interlayer insulating films (1) and (3) having contact holes (1a) and (3a), through which a surfaces of the source/drain region is partially exposed, is formed on the surface of silicon substrate (31). Contact holes (1a) and (3a) are filled with plug layer (9a). A capacitor (20) having a highly dielectric film (15) is formed such that it is electrically connected to source/drain region (25) through plug layer (9a). The interlayer insulating film is formed of a two-layer structure including a silicon oxide film (1) and a silicon nitride film (3). Silicon nitride film (3) and plug layer (9a) have the top surfaces flush with each other.

Inventors

  • 👤 Tomonori Okudaira
  • 👤 Keiichiro Kashihara

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 10:23
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 205 words
A semiconductor device, comprising: a semiconductor substrate having a main surface; an impurity region formed at said main surface of said semiconductor substrate; a first insulating film formed on said main surface of said semiconductor substrate to cover said impurity region and having a first hole reaching a portion of a surface of said impurity region; a second insulating film formed on said first insulating film, and having a second hole communicating with said first hole, said first and second holes having an open diameter extending from the top surface of said second insulating film to said impurity region; a buried conductive layer in contact with a portion of a surface of said impurity region, filling said first and second holes and having a surface substantially flush with the top surface of said second insulating film, said buried conductive layer having etch characteristics substantially equal to those of said second insulating film; a lower electrode layer in contact with said buried conductive layer and formed on the top surface of said second insulating film; a capacitor insulating layer covering said lower electrode layer and containing high permittivity dielectric material; and an upper electrode layer covering said lower electrode layer with said capacitor insulating layer therebetween.
Claim 2
Dependent Claim 205 words
A semiconductor device, comprising: a semiconductor substrate having a main surface; an impurity region formed at said main surface of said semiconductor substrate; a first insulating film formed on said main surface of said semiconductor substrate to cover said impurity region and having a first hole reaching a portion of a surface of said impurity region; a second insulating film formed on said first insulating film, and having a second hole communicating with said first hole, said first and second holes having an open diameter extending from the top surface of said second insulating film to said impurity region; a buried conductive layer in contact with a portion of a surface of said impurity region, filling said first and second holes and having a surface substantially flush with the top surface of said second insulating film, said buried conductive layer having etch characteristics substantially equal to those of said second insulating film; a lower electrode layer in contact with said buried conductive layer and formed on the top surface of said second insulating film; a capacitor insulating layer covering said lower electrode layer and containing high permittivity dielectric material; and an upper electrode layer covering said lower electrode layer with said capacitor insulating layer therebetween.
Claim 3
Dependent Claim 20 words
The semiconductor device according to claim 1, wherein said second insulating film is made of a material containing silicon nitride.
Claim 4
Dependent Claim 34 words
The semiconductor device according to claim 1, further comprising a barrier layer located between said lower electrode layer and said buried conductive layer and between said lower electrode layer and said second insulating film.
Claim 5
Dependent Claim 28 words
The semiconductor device according to claim 3, wherein said barrier layer has a multi-layer structure including a titanium layer, a titanium nitride layer and a titanium oxide layer.
Claim 6
Dependent Claim 51 words
The semiconductor device according to claim 1, wherein said capacitor insulating layer is made of at least a material selected from the group consisting of tantalum oxide (Ta 2 O 5 ), lead titanate zirconate (PZT), lanthan-lead titanate zirconate (PLZT), strontium titanate (STO), barium titanate (BTO) and barium strontium titanate (BST).
Claim 7
Dependent Claim 19 words
The semiconductor device according to claim 1, wherein said impurity region has a source/drain region of an MOS transistor.
Claim 8
Dependent Claim 30 words
The semiconductor device according to claim 1, wherein the diameter of the first and second holes is smaller than the minimum diameter which can be attained by conventional photolithographic techniques.

References Cited (Backward Citations)

US5272367A Cited
JPH03231431A Cited
US5335138A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-10-16 1999-04-17 1999-10-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-10-16 2003-04-17 2003-10-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-10-16 2007-04-17 2007-10-17 $7700.00 Window Closed / Lapsed

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