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Patent US5920775A successfully refreshed from Google Patents.
US5920775A
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US
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Method for forming a storage capacitor within an integrated circuit
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1996-02-23
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Granted: 1999-07-06
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Expires: 2016-02-23
Abstract
Abstract A method for forming a storage capacitor within an integrated circuit cell. There is first formed upon a semiconductor substrate an integrated circuit cell. The integrated circuit cell has formed therein a Field Effect Transistor (FET) which has an exposed source/drain electrode. The semiconductor substrate also has formed therein at least one other integrated circuit device which has at least one exposed contact electrode. There is then formed upon the semiconductor substrate a blanket conductor layer. The blanket conductor layer is then patterned to form a first portion of the blanket conductor layer and a second portion of the blanket conductor layer separate from each other. The first portion of the blanket conductor layer forms a patterned conductor layer contacting the exposed contact electrode of the other integrated circuit device. The second portion of the blanket conductor layer simultaneously forms a storage capacitor node contacting the exposed source/drain electrode of the Field Effect Transistor (FET). A storage capacitor within the integrated circuit cell may then be completed by forming a storage capacitor dielectric layer upon the storage capacitor node and subsequently forming a storage capacitor plate layer upon the storage capacitor dielectric layer.
Inventors
- 👤 Chao-Ming Koh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:46
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
176 words
A method for forming a storage capacitor node within an integrated circuit cell comprising: forming upon a semiconductor substrate: (a) an integrated circuit cell comprising a first Field Effect Transistor (FET), the first Field Effect Transistor (FET) having an exposed source/drain region; and, (b) at least one other integrated circuit device, the other integrated circuit device having at least one exposed contact electrode; forming then upon the semiconductor substrate a blanket first conductor layer; and, patterning the blanket first conductor layer to form a first portion of the blanket first conductor layer and a second portion of the blanket first conductor layer separate from each other, the first portion of the blanket first conductor layer forming a patterned first conductor layer contacting the exposed contact electrode of the other integrated circuit device and the second portion of the blanket first conductor layer simultaneously forming a storage capacitor node contacting the exposed source/drain region of the first Field Effect Transistor (FET), wherein the second portion of the blanket first conductor layer is formed with a "T" shape.
Claim 2
Independent Claim
176 words
A method for forming a storage capacitor node within an integrated circuit cell comprising: forming upon a semiconductor substrate: (a) an integrated circuit cell comprising a first Field Effect Transistor (FET), the first Field Effect Transistor (FET) having an exposed source/drain region; and, (b) at least one other integrated circuit device, the other integrated circuit device having at least one exposed contact electrode; forming then upon the semiconductor substrate a blanket first conductor layer; and, patterning the blanket first conductor layer to form a first portion of the blanket first conductor layer and a second portion of the blanket first conductor layer separate from each other, the first portion of the blanket first conductor layer forming a patterned first conductor layer contacting the exposed contact electrode of the other integrated circuit device and the second portion of the blanket first conductor layer simultaneously forming a storage capacitor node contacting the exposed source/drain region of the first Field Effect Transistor (FET), wherein the second portion of the blanket first conductor layer is formed with a "T" shape.
Claim 3
Dependent Claim
16 words
The method of claim 1 wherein the integrated circuit cell is a memory integrated circuit cell.
Claim 4
Dependent Claim
22 words
The method of claim 2 wherein the memory integrated circuit cell is a Dynamic Random Access Memory (DRAM) memory integrated circuit cell.
Claim 5
Dependent Claim
18 words
The method of claim 1 wherein the other integrated circuit device is a second Field Effect Transistor (FET).
Claim 6
Dependent Claim
16 words
The method of claim 1 wherein the blanket first conductor layer comprises a blanket tungsten layer.
Claim 7
Dependent Claim
36 words
The method of claim 1 wherein the horizontal portion of the "T" shape is from about 4000 to about 10000 angstroms in width and about 1000 to about 6000 angstroms in height over the semiconductor substrate.
Claim 8
Independent Claim
199 words
A method for forming a storage capacitor within an integrated circuit cell comprising: forming upon a semiconductor substrate: (a) an integrated circuit cell comprising a first Field Effect Transistor (FET), the first Field Effect Transistor (FET) having an exposed source/drain region; and, (b) at least one other integrated circuit device, the other integrated circuit device having at least one exposed contact electrode; forming then upon the semiconductor substrate a blanket first conductor layer; patterning the blanket first conductor layer to form a first portion of the blanket first conductor layer and a second portion of the blanket first conductor layer separate from each other, the first portion of the blanket first conductor layer forming a patterned first conductor layer contacting the contact electrode of the other integrated circuit device and the second portion of the blanket first conductor layer simultaneously forming a storage capacitor node contacting the exposed source/drain region of the first Field Effect Transistor (ET), wherein the second portion of the blanket first conductor layer is formed with a "T" shape; forming then upon the storage capacitor node a storage capacitor dielectric layer; and, forming then upon the storage capacitor dielectric layer a storage capacitor plate layer.
Claim 9
Independent Claim
199 words
A method for forming a storage capacitor within an integrated circuit cell comprising: forming upon a semiconductor substrate: (a) an integrated circuit cell comprising a first Field Effect Transistor (FET), the first Field Effect Transistor (FET) having an exposed source/drain region; and, (b) at least one other integrated circuit device, the other integrated circuit device having at least one exposed contact electrode; forming then upon the semiconductor substrate a blanket first conductor layer; patterning the blanket first conductor layer to form a first portion of the blanket first conductor layer and a second portion of the blanket first conductor layer separate from each other, the first portion of the blanket first conductor layer forming a patterned first conductor layer contacting the contact electrode of the other integrated circuit device and the second portion of the blanket first conductor layer simultaneously forming a storage capacitor node contacting the exposed source/drain region of the first Field Effect Transistor (ET), wherein the second portion of the blanket first conductor layer is formed with a "T" shape; forming then upon the storage capacitor node a storage capacitor dielectric layer; and, forming then upon the storage capacitor dielectric layer a storage capacitor plate layer.
Claim 10
Dependent Claim
16 words
The method of claim 7 wherein the integrated circuit cell is a memory integrated circuit cell.
Claim 11
Dependent Claim
22 words
The method of claim 8 wherein the integrated circuit memory cell is a Dynamic Random Access Memory (DRAM) memory integrated circuit cell.
Claim 12
Dependent Claim
16 words
The method of claim 7 wherein the blanket first conductor layer comprises a blanket tungsten layer.
Claim 13
Dependent Claim
36 words
The method of claim 7 wherein the horizontal portion of the "T" shape is from about 4000 to about 10000 angstroms in width and about 1000 to about 6000 angstroms in height over the semiconductor substrate.
Claim 14
Dependent Claim
20 words
The method of claim 7 wherein the storage capacitor dielectric layer is from about 85 to about 2000 angstroms thick.
Claim 15
Dependent Claim
39 words
The method of claim 7 wherein the storage capacitor dielectric layer is formed from a dielectric material chosen from the group of high permittivity dielectric materials consisting of tantalum oxide (Ta2O5), lead-zirconium titanates ((Pb,Zr)TiO3) (PZT) and barium-strontium titanates ((Ba,Sr)TiO3).
Claim 16
Dependent Claim
20 words
The method of claim 7 wherein the storage capacitor plate layer is from about 500 to about 2000 angstroms thick.
Claim 17
Dependent Claim
31 words
The method of claim 7 wherein the storage capacitor plate layer is formed from a conductor material chosen from the group of conductor materials consisting of titanium nitride, tungsten and platinum.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-05 | 2003-01-04 | 2003-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-05 | 2007-01-04 | 2007-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-05 | 2011-01-04 | 2011-07-06 | $7700.00 | Window Closed / Lapsed |