Method for fabricating dynamic random access memory with a flat topography and fewer photomasks

Claim 1

A method for fabricating dynamic random access memory (DRAM) having a flat topography on a semiconductor substrate, comprising the steps of: providing said semiconductor substrate having device areas surrounded and electrically isolated from each other by field oxide areas and further providing field effect transistors having gate electrodes formed from a patterned first polysilicon layer and having sidewall spacers formed from a first insulating layer and having source/drain contact areas adjacent to said gate electrodes in said device areas; depositing a second insulating layer having a planar surface; anisotropically etching openings in said second insulating layer to said source/drain contact areas and forming concurrently bit line contact openings and capacitor node contact openings for said field effect transistors; depositing a second polysilicon layer thereby filling said bit line contact openings and said capacitor node contact openings; planarizing said second polysilicon layer by partially etching back said second polysilicon layer; forming a silicide layer on said second polysilicon layer; depositing a third insulating layer on said silicide layer; forming bit lines extending over said bit line contact openings by patterning said third insulating layer, said silicide layer, and said second polysilicon layer, and concurrently leaving portions of said second polysilicon layer in said capacitor node contact openings, thereby forming capacitor node contacts for capacitors; depositing a conformal fourth insulating layer and anisotropically etching back to the surface of said second insulating layer thereby forming sidewall spacers on said bit lines; depositing a blanket third polysilicon layer on said second insulating layer and over and electrically contacting said capacitor node contacts formed from said second polysilicon layer; patterning said third polysilicon layer leaving portions over said capacitor node contacts and adjacent to said bit lines, thereby forming capacitor bottom electrodes; forming an interelectrode dielectric layer on said capacitor bottom electrodes; depositing a blanket fourth polysilicon layer on said interelectrode dielectric layer over said capacitor bottom electrodes and elsewhere on said substrate surface; patterning said fourth polysilicon layer leaving portions over said capacitor bottom electrodes and adjacent to said bit lines to form top electrodes, thereby forming said DRAM having said flat topography.

Claim 2

A method for fabricating dynamic random access memory (DRAM) having a flat topography on a semiconductor substrate, comprising the steps of: providing said semiconductor substrate having device areas surrounded and electrically isolated from each other by field oxide areas and further providing field effect transistors having gate electrodes formed from a patterned first polysilicon layer and having sidewall spacers formed from a first insulating layer and having source/drain contact areas adjacent to said gate electrodes in said device areas; depositing a second insulating layer having a planar surface; anisotropically etching openings in said second insulating layer to said source/drain contact areas and forming concurrently bit line contact openings and capacitor node contact openings for said field effect transistors; depositing a second polysilicon layer thereby filling said bit line contact openings and said capacitor node contact openings; planarizing said second polysilicon layer by partially etching back said second polysilicon layer; forming a silicide layer on said second polysilicon layer; depositing a third insulating layer on said silicide layer; forming bit lines extending over said bit line contact openings by patterning said third insulating layer, said silicide layer, and said second polysilicon layer, and concurrently leaving portions of said second polysilicon layer in said capacitor node contact openings, thereby forming capacitor node contacts for capacitors; depositing a conformal fourth insulating layer and anisotropically etching back to the surface of said second insulating layer thereby forming sidewall spacers on said bit lines; depositing a blanket third polysilicon layer on said second insulating layer and over and electrically contacting said capacitor node contacts formed from said second polysilicon layer; patterning said third polysilicon layer leaving portions over said capacitor node contacts and adjacent to said bit lines, thereby forming capacitor bottom electrodes; forming an interelectrode dielectric layer on said capacitor bottom electrodes; depositing a blanket fourth polysilicon layer on said interelectrode dielectric layer over said capacitor bottom electrodes and elsewhere on said substrate surface; patterning said fourth polysilicon layer leaving portions over said capacitor bottom electrodes and adjacent to said bit lines to form top electrodes, thereby forming said DRAM having said flat topography.

Claim 13

A method for fabricating dynamic random access memory (DRAM) having a flat topography on a semiconductor substrate, comprising the steps of: providing said semiconductor substrate having device areas surrounded and electrically isolated from each other by field oxide areas and further providing field effect transistors having gate electrodes formed from a patterned first polysilicon layer and having sidewall spacers formed from a first insulating layer and having source/drain contact areas adjacent to said gate electrodes in said device areas; depositing a second insulating layer having a planar surface formed by chemical/mechanical polishing; anisotropically etching openings in said second insulating layer to said source/drain contact areas and forming concurrently bit line contact openings and capacitor node contact openings for said field effect transistors; depositing a second polysilicon layer thereby filling said bit line contact openings and said capacitor node contact openings; planarizing said second polysilicon layer by partially etching back said second polysilicon layer; forming a tungsten silicide layer on said second polysilicon layer; depositing a third insulating layer on said tungsten silicide layer; forming bit lines extending over said bit line contact openings by patterning said third insulating layer, said tungsten silicide layer, and said second polysilicon layer, and concurrently leaving portions of said second polysilicon layer in said capacitor node contacts openings, thereby forming capacitor node contacts for capacitors; depositing a conformal fourth insulating layer and anisotropically etching back to the surface of said second insulating layer thereby forming sidewall spacers on said bit lines; depositing a blanket third polysilicon layer on said second insulating layer and over and electrically contacting said capacitor node contacts formed from said second polysilicon layer; patterning said third polysilicon layer leaving portions over said capacitor node contacts and adjacent to said bit lines, thereby forming capacitor bottom electrodes; forming an interelectrode dielectric layer on said capacitor bottom electrodes; depositing a blanket fourth polysilicon layer on said interelectrode dielectric layer over said capacitor bottom electrodes and elsewhere on said substrate surface; patterning said fourth polysilicon layer leaving portions over said capacitor bottom electrodes and adjacent to said bit lines and forming top electrodes, thereby forming said DRAM having said flat topography.

Claim 14

A method for fabricating dynamic random access memory (DRAM) having a flat topography on a semiconductor substrate, comprising the steps of: providing said semiconductor substrate having device areas surrounded and electrically isolated from each other by field oxide areas and further providing field effect transistors having gate electrodes formed from a patterned first polysilicon layer and having sidewall spacers formed from a first insulating layer and having source/drain contact areas adjacent to said gate electrodes in said device areas; depositing a second insulating layer having a planar surface formed by chemical/mechanical polishing; anisotropically etching openings in said second insulating layer to said source/drain contact areas and forming concurrently bit line contact openings and capacitor node contact openings for said field effect transistors; depositing a second polysilicon layer thereby filling said bit line contact openings and said capacitor node contact openings; planarizing said second polysilicon layer by partially etching back said second polysilicon layer; forming a tungsten silicide layer on said second polysilicon layer; depositing a third insulating layer on said tungsten silicide layer; forming bit lines extending over said bit line contact openings by patterning said third insulating layer, said tungsten silicide layer, and said second polysilicon layer, and concurrently leaving portions of said second polysilicon layer in said capacitor node contacts openings, thereby forming capacitor node contacts for capacitors; depositing a conformal fourth insulating layer and anisotropically etching back to the surface of said second insulating layer thereby forming sidewall spacers on said bit lines; depositing a blanket third polysilicon layer on said second insulating layer and over and electrically contacting said capacitor node contacts formed from said second polysilicon layer; patterning said third polysilicon layer leaving portions over said capacitor node contacts and adjacent to said bit lines, thereby forming capacitor bottom electrodes; forming an interelectrode dielectric layer on said capacitor bottom electrodes; depositing a blanket fourth polysilicon layer on said interelectrode dielectric layer over said capacitor bottom electrodes and elsewhere on said substrate surface; patterning said fourth polysilicon layer leaving portions over said capacitor bottom electrodes and adjacent to said bit lines and forming top electrodes, thereby forming said DRAM having said flat topography.