US5534458A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor device with high dielectric capacitor having sidewall spacers
Assignee: Renesas Electronics Corp
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Filing: 1995-05-17
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Granted: 1996-07-09
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Expires: 2015-05-17
Abstract
Abstract According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.
Inventors
- 👤 Tomonori Okudaira
- 👤 Takeharu Kuroiwa
- 👤 Nobuo Fujiwara
- 👤 Keiichiro Kashihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:32
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/682; H10P; H10P14/00; H10P14/40; Y; Y10; Y10S; Y10S257/00; Y10S257/915; Y10S438/00; Y10S438/978
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
229 words
A method of manufacturing a semiconductor device comprising the steps of: forming an impurity region on a main surface of a semiconductor substrate, forming an interlayer insulation film on the main surface of the semiconductor substrate to cover said impurity region, forming a contact hole in said interlayer insulation film reaching said impurity region, forming a buried conductive layer, filling said contact hole, in contact with said impurity region, and having a top face lower in level than a top face of said interlayer insulation film, forming a lower electrode layer on said interlayer insulation film to come into contact with said buried conductive layer, forming a first sidewall spacer at an edge face portion of said lower electrode layer, from a top face corner of said lower electrode layer to the top face of said interlayer insulation film, forming a second sidewall spacer on said lower electrode layer in a recess portion defined by a sidewall of said contact hole and said buried conductive layer, from a top face corner of said lower electrode layer formed on said interlayer insulation film to said lower electrode layer formed on said buried conductive layer, forming a high dielectric film of a high dielectric constant material to cover said lower electrode layer, and said first and second sidewall spacers, and forming an upper electrode layer to cover said high dielectric film.
Claim 2
Independent Claim
229 words
A method of manufacturing a semiconductor device comprising the steps of: forming an impurity region on a main surface of a semiconductor substrate, forming an interlayer insulation film on the main surface of the semiconductor substrate to cover said impurity region, forming a contact hole in said interlayer insulation film reaching said impurity region, forming a buried conductive layer, filling said contact hole, in contact with said impurity region, and having a top face lower in level than a top face of said interlayer insulation film, forming a lower electrode layer on said interlayer insulation film to come into contact with said buried conductive layer, forming a first sidewall spacer at an edge face portion of said lower electrode layer, from a top face corner of said lower electrode layer to the top face of said interlayer insulation film, forming a second sidewall spacer on said lower electrode layer in a recess portion defined by a sidewall of said contact hole and said buried conductive layer, from a top face corner of said lower electrode layer formed on said interlayer insulation film to said lower electrode layer formed on said buried conductive layer, forming a high dielectric film of a high dielectric constant material to cover said lower electrode layer, and said first and second sidewall spacers, and forming an upper electrode layer to cover said high dielectric film.
Claim 3
Dependent Claim
47 words
The method of manufacturing a semiconductor device according to claim 1, wherein said step of forming said first and second sidewall spacers comprise the steps of forming a silicon oxide film of 800-1200Å to cover said lower electrode layer, and dry etching said silicon oxide film anisotropically.
References Cited (Backward Citations)
US5046043A
Cited
US5248628A
Cited
JPH03256358A
Cited
JPH0463471A
Cited
JPH0499057A
Cited
US5332684A
Cited
US5401680A
Cited
US5187638A
Cited
US5335138A
Cited
US5444010A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-09 | 2000-01-08 | 2000-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-09 | 2004-01-08 | 2004-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-09 | 2008-01-08 | 2008-07-09 | $7700.00 | Window Closed / Lapsed |