US5279989A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for forming miniature contacts of highly integrated semiconductor devices
Assignee: SK Hynix Inc
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Filing: 1993-03-01
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Granted: 1994-01-18
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Expires: 2013-03-01
Abstract
Abstract A method of forming miniature contacts over the sources and drains of the MOSFETs of a highly integrated semiconductor device which includes the steps of: applying a thick insulation layer over the MOSFETs, applying a first polysilicon layer, a subsequent insulation layer and a photoresist film having predetermined thickness over the original thick insulation layer. The photoresist film is removed at its portions disposed above the sources and drains to form a photoresist film pattern and the subsequent insulation layer is etched in order to form an insulation pattern. The first polysilicon layer is etched using the insulation layer pattern as a mask, in order to form a first polysilicon layer pattern. The insulation layer pattern is removed and the thick insulation layer is etched using the first polysilicon layer pattern as a mask. A base insulation layer is etched, thus forming contact holes through which the sources and drains are exposed. Subsequently, a second polysilicon layer with a smooth upper surface is deposited over first polysilicon layer pattern and the contact holes, and a predetermined thickness portion of the second polysilicon layer and the first polysilicon layer pattern are removed thus form contact pads respectively connected to the sources and drains. Conductive layers can then be applied to the contact pads for predetermined electrodes or wirings.
Inventors
- 👤 Jeong Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:04
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/031; H10W20/069; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/0335; H10B12/30; H10B12/48; H10B12/482; H10B12/485; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0149; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085; H10W20/056
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
402 words
A method for forming contacts of a highly integrated semiconductor device comprising the steps of forming over a silicon substrate an element isolation oxide film, a gate oxide film, and a plurality of MOSFETs each including gate electrodes, a source and a drain, forming a first insulation layer over the gate electrodes, removing partially the first insulation layer at its portions disposed over the sources and drains of said plurality of MOSFETs to form contact holes, and forming a conductive layer in contact with the sources and drains exposed through the contact holes, the method comprising the further step of forming miniature contacts over the sources and drains, said further step comprising the steps of: coating a thick second insulation layer as a smoothing layer over the first insulation layer including the MOSFETs and coating over the second insulation layer a first polysilicon layer, a third insulation layer and a photoresist film, in this order; removing the photoresist film at its portions disposed above the sources and drains to form a photoresist film pattern and etching the third insulation layer at its portions exposed through the removed portions of the photoresist film to form a third insulation layer pattern; removing the photoresist film pattern and forming spacers of a fourth insulation layer on side walls of the third insulation layer pattern; etching the first polysilicon layer at its portions exposed through the removed portions of the third insulation layer, under a condition of using both the third insulation layer pattern and the fourth insulation layer spacers as a mask, to form a first polysilicon layer pattern; removing the third insulation layer pattern and the fourth insulation layer spacers, etching the second insulation layer at its portion exposed through the removed third insulation layer pattern and fourth insulation layer spacers, under a condition of using the first polysilicon layer pattern as a mask, and etching the first insulation layer at its portion exposed through the etched portions of the second insulation layer, to form contact holes through which the sources and drains are exposed; depositing over the contact holes and the first polysilicon layer pattern a second polysilicon layer with a smooth upper surface and removing a portion of the second polysilicon layer and the first polysilicon layer pattern to form contact pads respectively connected to the sources and drains; and applying conductive layers for selected electrodes or wirings to the contact pads.
Claim 2
Independent Claim
402 words
A method for forming contacts of a highly integrated semiconductor device comprising the steps of forming over a silicon substrate an element isolation oxide film, a gate oxide film, and a plurality of MOSFETs each including gate electrodes, a source and a drain, forming a first insulation layer over the gate electrodes, removing partially the first insulation layer at its portions disposed over the sources and drains of said plurality of MOSFETs to form contact holes, and forming a conductive layer in contact with the sources and drains exposed through the contact holes, the method comprising the further step of forming miniature contacts over the sources and drains, said further step comprising the steps of: coating a thick second insulation layer as a smoothing layer over the first insulation layer including the MOSFETs and coating over the second insulation layer a first polysilicon layer, a third insulation layer and a photoresist film, in this order; removing the photoresist film at its portions disposed above the sources and drains to form a photoresist film pattern and etching the third insulation layer at its portions exposed through the removed portions of the photoresist film to form a third insulation layer pattern; removing the photoresist film pattern and forming spacers of a fourth insulation layer on side walls of the third insulation layer pattern; etching the first polysilicon layer at its portions exposed through the removed portions of the third insulation layer, under a condition of using both the third insulation layer pattern and the fourth insulation layer spacers as a mask, to form a first polysilicon layer pattern; removing the third insulation layer pattern and the fourth insulation layer spacers, etching the second insulation layer at its portion exposed through the removed third insulation layer pattern and fourth insulation layer spacers, under a condition of using the first polysilicon layer pattern as a mask, and etching the first insulation layer at its portion exposed through the etched portions of the second insulation layer, to form contact holes through which the sources and drains are exposed; depositing over the contact holes and the first polysilicon layer pattern a second polysilicon layer with a smooth upper surface and removing a portion of the second polysilicon layer and the first polysilicon layer pattern to form contact pads respectively connected to the sources and drains; and applying conductive layers for selected electrodes or wirings to the contact pads.
Claim 3
Dependent Claim
19 words
The method in accordance with claim 1, wherein the second and third insulation layers are comprised of oxide layers.
Claim 4
Dependent Claim
55 words
The method in accordance with claim 1, wherein the step of forming the fourth insulation layer spacers comprises the steps of coating the fourth insulation layer over the third insulation layer pattern and etching the fourth insulation layer to form the fourth insulation layer spacers on the side walls of the third insulation layer pattern.
Claim 5
Dependent Claim
18 words
The method in accordance with claim 3, wherein the fourth insulation layer is comprised of an oxide layer.
Claim 6
Dependent Claim
96 words
The method in accordance with claim 1, further comprising the steps of coating a fifth insulation layer over the entire exposed upper surface of the resultant structure obtained after the formation of the contact pads, removing portions of the fifth insulation layer to expose the contact pads therethrough, depositing a conductive layer for a bit line over the resultant entire exposed surface defined after the removal of the fifth insulation layer, and forming the bit line over and in contact with a corresponding one of the exposed contact pads by use of a mask pattern process.
Claim 7
Dependent Claim
47 words
The method in accordance with claim 5, further comprising the steps of coating a sixth insulation layer as a bit line insulating layer after the formation of the bit line, and forming storage capacity electrodes over and in contact with corresponding ones of the exposed contact pads.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-17 | 1997-07-19 | 1998-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-17 | 2001-07-19 | 2002-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-17 | 2005-07-19 | 2006-01-18 | $7700.00 | Window Closed / Lapsed |