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Semiconductor device having various threshold voltages and manufacturing same

Assignee: Sony Corp
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Filing: 1997-07-10
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Granted: 1999-06-08
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Expires: 2017-07-10
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Abstract

Abstract An impurity for adjusting a threshold voltage is ion-implanted using, as masks, a resist for forming P - -type diffusion layers, a resist for forming N + -type diffusion layers and N-type diffusion layers and a resist for forming P + -type diffusion layers and N-type diffusion layers. For this reason, a semiconductor device including first to third N-channel transistors and first and second P-channel transistors, all of which respectively have different threshold voltages, can be manufactured without using an additional resist except for the above resists. Therefore, an operating margin at a low voltage can be increased and data retention characteristics can be improved in a memory without causing an increase in cost, an increase in power consumption and the like.

Inventors

  • 👤 Hideaki Kuroda

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 20:42
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10D84/8312; H10D84/85; H10D84/856; H10P; H10P30/00; H10P30/20; H10P30/22; H10D84/8311

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 204 words
A semiconductor device comprising: a first transistor comprised of first diffusion layers which are exclusively comprised of a first conductivity type; a second transistor comprised of second diffusion layers of said first conductivity type in contact with a channel portion of said second transistor and third diffusion layers of said first conductivity type in contact with said second diffusion layers on a side opposing said channel portion of said second transistor; a third transistor comprised of fourth diffusion layers of a second conductivity type in contact with a channel portion of said third transistor and fifth diffusion layers of said second conductivity type in contact with said fourth diffusion layers on a side opposing said channel portion of said third transistor; wherein a concentration of said first diffusion layers is substantially the same as a concentration of said second diffusion layers and concentration of said third diffusion layers is higher than said first and second diffusion layers, and a concentration of said fifth diffusion layers is higher than said fourth diffusion layers; and further wherein said first, second and third transistors each have a different first conductivity type impurity concentration on the surface of the channel portions of said first, second and third transistors.
Claim 2
Dependent Claim 204 words
A semiconductor device comprising: a first transistor comprised of first diffusion layers which are exclusively comprised of a first conductivity type; a second transistor comprised of second diffusion layers of said first conductivity type in contact with a channel portion of said second transistor and third diffusion layers of said first conductivity type in contact with said second diffusion layers on a side opposing said channel portion of said second transistor; a third transistor comprised of fourth diffusion layers of a second conductivity type in contact with a channel portion of said third transistor and fifth diffusion layers of said second conductivity type in contact with said fourth diffusion layers on a side opposing said channel portion of said third transistor; wherein a concentration of said first diffusion layers is substantially the same as a concentration of said second diffusion layers and concentration of said third diffusion layers is higher than said first and second diffusion layers, and a concentration of said fifth diffusion layers is higher than said fourth diffusion layers; and further wherein said first, second and third transistors each have a different first conductivity type impurity concentration on the surface of the channel portions of said first, second and third transistors.

References Cited (Backward Citations)

US4937645A Cited
US4845047A Cited
US4753898A Cited
US5081515A Cited
US5399514A Cited
JPH0582751A Cited
EP1041112A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-06-07 2002-12-07 2003-06-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-06-07 2006-12-07 2007-06-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-06-07 2010-12-07 2011-06-08 $7700.00 Window Closed / Lapsed

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