Method of producing cylindrical storage node of stacked capacitor in memory cell

Claim 1

A method of producing a cylindrical storage node of a capacitor in a semiconductor memory cell having a MOS transistor coupled with said capacitor, the method comprising the steps of: (a) forming a first dielectric film, said first dielectric film serving as an etch stop film, on an interlayer insulator laid over a semiconductor substrate in which said transistor is already fabricated; (b) forming a second dielectric film, said second dielectric film serving as a planarizing film, on said first dielectric film and planarizing the surface of the second dielectric film; (c) forming a contact hole, said contact hole reaching one of source and drain region of said transistor, through said first and second dielectric films and said interlayer insulator and filling the contact hole with a conductor to provide a storage node contact; (d) removing said second dielectric film by etching to expose said first dielectric film after forming the storage node contact of step c; (e) depositing a first conductor film on said first dielectric film, the first conductor film being in contact with said storage node contact; (f) depositing third dielectric film over said first conductor film and patterning the third dielectric film so as to provide a cylindrical wall face on said first conductor film, wherein said third dielectric film is substantially thicker than other dielectric films; (g) forming a second conductor film as a cylindrical sidewall on said cylindrical wall face of said third dielectric film; and (h) completely removing said third dielectric film by etching.

Claim 2

A method of producing a cylindrical storage node of a capacitor in a semiconductor memory cell having a MOS transistor coupled with said capacitor, the method comprising the steps of: (a) forming a first dielectric film, said first dielectric film serving as an etch stop film, on an interlayer insulator laid over a semiconductor substrate in which said transistor is already fabricated; (b) forming a second dielectric film, said second dielectric film serving as a planarizing film, on said first dielectric film and planarizing the surface of the second dielectric film; (c) forming a contact hole, said contact hole reaching one of source and drain region of said transistor, through said first and second dielectric films and said interlayer insulator and filling the contact hole with a conductor to provide a storage node contact; (d) removing said second dielectric film by etching to expose said first dielectric film after forming the storage node contact of step c; (e) depositing a first conductor film on said first dielectric film, the first conductor film being in contact with said storage node contact; (f) depositing third dielectric film over said first conductor film and patterning the third dielectric film so as to provide a cylindrical wall face on said first conductor film, wherein said third dielectric film is substantially thicker than other dielectric films; (g) forming a second conductor film as a cylindrical sidewall on said cylindrical wall face of said third dielectric film; and (h) completely removing said third dielectric film by etching.