Method of manufacture of coaxial capacitor for dram memory cell and cell manufactured thereby

Claim 1

A method of fabricating a dynamic random access memory having a capacitor comprising: selectively forming field oxide areas on a surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices having gate electrode structures and source/drain structures; forming a gate dielectric layer on said substrate in said device areas; depositing a first layer of polysilicon on said field oxide areas and said device areas; removing portions of said first polysilicon layer while leaving portions thereof for said gate electrode structures in said device areas, and portions over said field oxide areas; forming said source/drain structures within said device areas of said semiconductor substrate associated with said gate electrode structures; forming a planarization silicon oxide layer over sad device areas and said field oxide areas, forming an etch stop layer over said planarization layer, forming a first portion of a lower capacitor plate doped polysilicon layer over said planarization layer, forming a glass layer on said first portion, forming a contact opening to said source/drain structures by etching through said glass layer, said first portion and etch stop and planarization layers therebelow down to one of said source/drain structures, forming a second portion of said lower capacitor plate comprising a polysilicon plug completely within said glass layer by etching a doped polysilicon layer formed over said substrate and through said contact opening into electrical and mechanical contact with one of said source/drain structures, said second portion having exposed sidewalls and a top surface extending above surface of said first portion of said lower capacitor plate after removing said glass layer, forming sacrificial spacer structures adjacent to said exposed sidewalls of said second portion of said lower capacitor plate, depositing a third portion of said lower capacitor plate polysilicon layer over said substrate including said sacrificial spacer structures and said first portion and said second portion into electrical and mechanical contact therewith, and providing doping thereof, etching back said third portion of said lower capacitor plate down to said etch stop layer and exposing said sacrificial spacer structures leaving upright elements from said third portion adjacent to said sacrificial spacer structures, then etching away said sacrificial spacer structures, forming a blanket interconductor dielectric layer over said substrate after etching away said sacrificial spacer structures providing an exposed surface of said interconductor dielectric layer, depositing an upper capacitor plate over said exposed interconductor dielectric layer, said upper capacitor plate extending between said second and third portions.

Claim 2

A method of fabricating a dynamic random access memory having a capacitor comprising: selectively forming field oxide areas on a surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices having gate electrode structures and source/drain structures; forming a gate dielectric layer on said substrate in said device areas; depositing a first layer of polysilicon on said field oxide areas and said device areas; removing portions of said first polysilicon layer while leaving portions thereof for said gate electrode structures in said device areas, and portions over said field oxide areas; forming said source/drain structures within said device areas of said semiconductor substrate associated with said gate electrode structures; forming a planarization silicon oxide layer over sad device areas and said field oxide areas, forming an etch stop layer over said planarization layer, forming a first portion of a lower capacitor plate doped polysilicon layer over said planarization layer, forming a glass layer on said first portion, forming a contact opening to said source/drain structures by etching through said glass layer, said first portion and etch stop and planarization layers therebelow down to one of said source/drain structures, forming a second portion of said lower capacitor plate comprising a polysilicon plug completely within said glass layer by etching a doped polysilicon layer formed over said substrate and through said contact opening into electrical and mechanical contact with one of said source/drain structures, said second portion having exposed sidewalls and a top surface extending above surface of said first portion of said lower capacitor plate after removing said glass layer, forming sacrificial spacer structures adjacent to said exposed sidewalls of said second portion of said lower capacitor plate, depositing a third portion of said lower capacitor plate polysilicon layer over said substrate including said sacrificial spacer structures and said first portion and said second portion into electrical and mechanical contact therewith, and providing doping thereof, etching back said third portion of said lower capacitor plate down to said etch stop layer and exposing said sacrificial spacer structures leaving upright elements from said third portion adjacent to said sacrificial spacer structures, then etching away said sacrificial spacer structures, forming a blanket interconductor dielectric layer over said substrate after etching away said sacrificial spacer structures providing an exposed surface of said interconductor dielectric layer, depositing an upper capacitor plate over said exposed interconductor dielectric layer, said upper capacitor plate extending between said second and third portions.

Claim 11

A method of fabricating a dynamic random access memory having a capacitor comprising: selectively forming field oxide areas on a surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices having gate electrode structures and source/drain structures; forming a gate dielectric layer on said substrate in said device areas; depositing a first layer of polysilicon on said field oxide areas and said device areas; removing portions of said first polysilicon layer while leaving portions thereof for said gate electrode structures in said device areas, and portions over said field oxide areas; forming said source/drain structures within said device areas of said semiconductor substrate associated with said gate electrode structures; forming a planarization silicon oxide layer over said device areas and said field oxide areas, forming an etch stop layer over said planarization layer, forming a first portion of a lower capacitor plate doped polysilicon layer over said planarization layer having a thickness between about 500 Å and about 1,000 Å, forming a glass layer formed by a TEOS process on said first portion having a thickness between about 5,000 Å and about 10,000 Å, forming a contact opening to said source/drain structures by etching through said glass layer, said first potion of said lower capacitor layer and etch stop and planarization layers therebelow down to one of said source/drain structures, forming a second portion of said lower capacitor plate comprising a polysilicon plug completely within said glass layer by etching a doped polysilicon layer formed over said substrate and through said contact opening into electrical and mechanical contact with one of said source/drain structures, said second portion having exposed sidewalls and a top surface extending above a surface of said first portion of said lower capacitor plate after removing said glass layer, forming sacrificial spacer structures adjacent to said exposed sidewalls of said second portion of said lower capacitor plate, depositing a third portion of said lower capacitor plate doped polysilicon layer over said substrate including said sacrificial spacer structures and said first portion and said second portion into electrical and mechanical contact therewith, and providing doping thereof, etching back said third portion of said lower capacitor plate down to said etch stop layer and exposing said sacrificial spacer structures leaving upright elements from said third portion adjacent to said sacrificial spacer structures, then etching away said sacrificial spacer structures, forming a blanket interconductor NO dielectric layer over said substrate after etching away said sacrificial spacer structures providing an exposed surface of said interconductor dielectric layer, depositing an upper capacitor plate extending between said second and third portions, said upper capacitor plate comprising a doped polysilicon layer over said exposed interconductor NO dielectric layer.

Claim 12

A method of fabricating a dynamic random access memory having a capacitor comprising: selectively forming field oxide areas on a surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices having gate electrode structures and source/drain structures; forming a gate dielectric layer on said substrate in said device areas; depositing a first layer of polysilicon on said field oxide areas and said device areas; removing portions of said first polysilicon layer while leaving portions thereof for said gate electrode structures in said device areas, and portions over said field oxide areas; forming said source/drain structures within said device areas of said semiconductor substrate associated with said gate electrode structures; forming a planarization silicon oxide layer over said device areas and said field oxide areas, forming an etch stop layer over said planarization layer, forming a first portion of a lower capacitor plate doped polysilicon layer over said planarization layer having a thickness between about 500 Å and about 1,000 Å, forming a glass layer formed by a TEOS process on said first portion having a thickness between about 5,000 Å and about 10,000 Å, forming a contact opening to said source/drain structures by etching through said glass layer, said first potion of said lower capacitor layer and etch stop and planarization layers therebelow down to one of said source/drain structures, forming a second portion of said lower capacitor plate comprising a polysilicon plug completely within said glass layer by etching a doped polysilicon layer formed over said substrate and through said contact opening into electrical and mechanical contact with one of said source/drain structures, said second portion having exposed sidewalls and a top surface extending above a surface of said first portion of said lower capacitor plate after removing said glass layer, forming sacrificial spacer structures adjacent to said exposed sidewalls of said second portion of said lower capacitor plate, depositing a third portion of said lower capacitor plate doped polysilicon layer over said substrate including said sacrificial spacer structures and said first portion and said second portion into electrical and mechanical contact therewith, and providing doping thereof, etching back said third portion of said lower capacitor plate down to said etch stop layer and exposing said sacrificial spacer structures leaving upright elements from said third portion adjacent to said sacrificial spacer structures, then etching away said sacrificial spacer structures, forming a blanket interconductor NO dielectric layer over said substrate after etching away said sacrificial spacer structures providing an exposed surface of said interconductor dielectric layer, depositing an upper capacitor plate extending between said second and third portions, said upper capacitor plate comprising a doped polysilicon layer over said exposed interconductor NO dielectric layer.

Claim 22

A method of fabricating a dynamic random access memory having a capacitor comprising: selectively forming field oxide areas on a surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices having gate electrode structures and source/drain structures; forming a gate dielectric layer on said substrate in said device areas; depositing a first layer of polysilicon on said field oxide areas and said device areas; removing portions of said first polysilicon layer while leaving portions thereof for said gate electrode structures in said device areas, and portions over said field oxide areas; forming said source/drain structures within said device areas of said semiconductor substrate associated with said gate electrode structures; forming a planarization silicon oxide layer over said device areas and said field oxide areas, forming an etch stop layer over said planarization layer, forming a first portion of a lower capacitor plate doped polysilicon layer over said planarization layer, forming a first glass layer on said first portion, forming a contact opening to said source/drain structures by etching through said first glass layer, said first portion layer and etch stop and planarization layers therebelow down to one of said source/drain structures, forming a second portion of said lower capacitor plate comprising a polysilicon plug completely within said first glass layer by etching a doped polysilicon layer formed over said substrate and through said contact opening into electrical and mechanical contact with one of said source/drain structures, said second portion having exposed sidewalls and a top surface extending above a surface of said first portion of said lower capacitor plate after removing said first glass layer, forming sacrificial glass spacer structures adjacent to said exposed sidewalls of said second portion of said lower capacitor plate, depositing a third portion of said lower capacitor plate doped polysilicon layer over said substrate including said sacrificial glass spacer structures and said first portion and said second portion into electrical and mechanical contact therewith, and providing doping thereof, etching back said third portion of said lower capacitor plate down to said etch stop layer and exposing said sacrificial glass spacer structures leaving upright elements from said third portion adjacent to said sacrificial glass spacer structures, then etching away said sacrificial glass spacer structures, forming a blanket interconductor dielectric layer over said substrate after etching away said sacrificial glass spacer structures providing an exposed surface of said interconductor dielectric layer, depositing an upper capacitor plate extending between said second and third portions, said upper capacitor plate comprising a doped polysilicon layer over said exposed interconductor dielectric layer.

Claim 23

A method of fabricating a dynamic random access memory having a capacitor comprising: selectively forming field oxide areas on a surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices having gate electrode structures and source/drain structures; forming a gate dielectric layer on said substrate in said device areas; depositing a first layer of polysilicon on said field oxide areas and said device areas; removing portions of said first polysilicon layer while leaving portions thereof for said gate electrode structures in said device areas, and portions over said field oxide areas; forming said source/drain structures within said device areas of said semiconductor substrate associated with said gate electrode structures; forming a planarization silicon oxide layer over said device areas and said field oxide areas, forming an etch stop layer over said planarization layer, forming a first portion of a lower capacitor plate doped polysilicon layer over said planarization layer, forming a first glass layer on said first portion, forming a contact opening to said source/drain structures by etching through said first glass layer, said first portion layer and etch stop and planarization layers therebelow down to one of said source/drain structures, forming a second portion of said lower capacitor plate comprising a polysilicon plug completely within said first glass layer by etching a doped polysilicon layer formed over said substrate and through said contact opening into electrical and mechanical contact with one of said source/drain structures, said second portion having exposed sidewalls and a top surface extending above a surface of said first portion of said lower capacitor plate after removing said first glass layer, forming sacrificial glass spacer structures adjacent to said exposed sidewalls of said second portion of said lower capacitor plate, depositing a third portion of said lower capacitor plate doped polysilicon layer over said substrate including said sacrificial glass spacer structures and said first portion and said second portion into electrical and mechanical contact therewith, and providing doping thereof, etching back said third portion of said lower capacitor plate down to said etch stop layer and exposing said sacrificial glass spacer structures leaving upright elements from said third portion adjacent to said sacrificial glass spacer structures, then etching away said sacrificial glass spacer structures, forming a blanket interconductor dielectric layer over said substrate after etching away said sacrificial glass spacer structures providing an exposed surface of said interconductor dielectric layer, depositing an upper capacitor plate extending between said second and third portions, said upper capacitor plate comprising a doped polysilicon layer over said exposed interconductor dielectric layer.