US5346844A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating semiconductor memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-06-30
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Granted: 1994-09-13
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Expires: 2012-06-30
Abstract
Abstract A semiconductor memory device and fabricating method thereof including one transistor consisting of a source, a drain and a gate electrode, a bit line in contact with the drain region of the transistor via a first contact hole, a storage electrode in contact with the source region of the transistor via a second contact hole, a first planarized insulating layer formed under the bit line and a second planarized insulating layer formed under the storage electrode, whereby the material layer formed under the conductive layers, e.g., the bit line and storage electrode, is planarized to prevent stringers created due to surface indentations. Further, after a spacer is formed directly on the side walls of contact hole or on the side walls of a pattern for forming the contact hole, the contact hole is formed to prevent the contact between conductive layers, as a result, improving the memory device's reliability and being advantageous in realizing high density.
Inventors
- 👤 Hyun-jin Cho
- 👤 Taek-Yong Jang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:49
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/0335; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/042; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/716; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; H10W20/40; H10W20/495
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
138 words
A method for fabricating a semiconductor memory device comprising the steps of: forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source, drain and gate electrode is formed; forming a first contact hole by partly removing said first insulating layer formed on said drain region; forming a first spacer on an inner side wall of said first contact hole; forming a bit line connected to said drain region via said first contact hole; forming a second planarized insulating layer on the overall resultant structure; forming a second contact hole by partly removing said first and second insulating layers formed on said source region; forming a second spacer on an inner side wall of said second contact hole; and forming a storage electrode connected to said source region via said second contact hole.
Claim 2
Independent Claim
138 words
A method for fabricating a semiconductor memory device comprising the steps of: forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source, drain and gate electrode is formed; forming a first contact hole by partly removing said first insulating layer formed on said drain region; forming a first spacer on an inner side wall of said first contact hole; forming a bit line connected to said drain region via said first contact hole; forming a second planarized insulating layer on the overall resultant structure; forming a second contact hole by partly removing said first and second insulating layers formed on said source region; forming a second spacer on an inner side wall of said second contact hole; and forming a storage electrode connected to said source region via said second contact hole.
Claim 3
Dependent Claim
35 words
A method for fabricating a semiconductor memory device as claimed in claim 1, wherein a step of forming an insulating layer is additionally carried out after said step of forming the transistor on the substrate.
Claim 4
Dependent Claim
29 words
A method for fabricating a semiconductor memory device as claimed in claim 2, wherein an insulating material such as HTO is used for the material of said insulating layers.
Claim 5
Dependent Claim
148 words
A method for fabricating a semiconductor memory device as claimed in claim 1, wherein said step Of forming the first spacer on the inner side walls of said contact hole is divided into a step of covering a first insulating material having the different etching rate from that of said first insulating layer with respect to a first anisotropical etching on the overall resultant structure and a step of carrying out said first anisotropical etching on the overall resultant structure, and said step of forming the second spacer on the inner side walls of said second contact hole is divided into a step of covering a second insulating material having the different etching rate from that of said second insulating layer with respect to a second anisotropical etching on the overall resultant structure and a step of carrying out said second anisotropical etching on the overall resultant structure.
Claim 6
Dependent Claim
41 words
A method for fabricating a semiconductor memory device as claimed in claim 4, wherein said first and second insulating layers are formed of one or a combination of BPSG, a TEOS oxide layer, silicon nitride, SOG and a CVD oxide layer.
Claim 7
Dependent Claim
44 words
A method for fabricating a semiconductor memory device as claimed in claim 5, wherein said first and second spacers are formed of one or a combination of a CVD oxide layer, a nitride insulating material, undoped polysilicon, monocrystal silicon and a PE-TEOS oxide layer.
Claim 8
Independent Claim
273 words
A method for fabricating a semiconductor memory device comprising the steps of: forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source, drain and gate electrode is formed; forming a first contact hole by partly removing said first insulating layer formed on said drain region, said first contact hole removing step including the steps of: forming a first material layer where a first pattern for forming said first contact hole is formed, on the overall resultant structure where said first insulating layer is formed, forming a third spacer on the inner side walls of said first pattern, and anisotropically etching on the resultant structure using said first pattern and third spacer as an etching mask and taking the surface of said substrate as its etching end point; forming a bit line connected to said drain region via said first contact hole; forming a second planarized insulating layer on the overall resultant structure; forming a second contact hole by partly removing said first and second insulating layers formed on said source region, said second hole forming step including the steps of: forming a second material layer where a second pattern for forming said second contact hole is formed on the overall resultant structure where said second insulating layer is formed, forming a fourth spacer on the inner side wall of said second pattern, and anisotropically etching on the resultant structure using said second pattern and fourth spacer as an etching mask and taking the surface of said substrate as its etching end point; and forming a storage electrode connected to said source region via said second contact hole.
Claim 9
Independent Claim
273 words
A method for fabricating a semiconductor memory device comprising the steps of: forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source, drain and gate electrode is formed; forming a first contact hole by partly removing said first insulating layer formed on said drain region, said first contact hole removing step including the steps of: forming a first material layer where a first pattern for forming said first contact hole is formed, on the overall resultant structure where said first insulating layer is formed, forming a third spacer on the inner side walls of said first pattern, and anisotropically etching on the resultant structure using said first pattern and third spacer as an etching mask and taking the surface of said substrate as its etching end point; forming a bit line connected to said drain region via said first contact hole; forming a second planarized insulating layer on the overall resultant structure; forming a second contact hole by partly removing said first and second insulating layers formed on said source region, said second hole forming step including the steps of: forming a second material layer where a second pattern for forming said second contact hole is formed on the overall resultant structure where said second insulating layer is formed, forming a fourth spacer on the inner side wall of said second pattern, and anisotropically etching on the resultant structure using said second pattern and fourth spacer as an etching mask and taking the surface of said substrate as its etching end point; and forming a storage electrode connected to said source region via said second contact hole.
References Cited (Backward Citations)
US4565712A
Cited
US5079181A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-12 | 1998-03-14 | 1998-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-12 | 2002-03-14 | 2002-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-12 | 2006-03-14 | 2006-09-13 | $7700.00 | Window Closed / Lapsed |