US5726086A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making self-aligned cylindrical capacitor structure of stack DRAMS
Assignee: Promos Technologies Inc
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Filing: 1996-11-18
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Granted: 1998-03-10
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Expires: 2016-11-18
Abstract
Abstract The present invention discloses a method of fabricating self-aligned cylindrical capacitor in stack Dynamic Random Access Memory (Stack DRAM) cells. The polysilicon stud is filled in the contact window of the source region of a metal-oxide-semiconductor field effect transistor (MOSFET). Then the polysilicon spacers are formed on the sidewalls of the first polysilicon stud. The cylindrical capacitor storage node of the DRAM capacitor of the present invention has much greater surface area so as to increase the capacitance value of the DRAM capacitor, that can achieve high packing density of the integrated circuit devices. Furthermore, this new process only needs one lithography photomask to open contact window compared with the conventional process which needs two lithography photomasks, that further reduces the production cost.
Inventors
- 👤 Chung-Cheng Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 11:28
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/042; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/716
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
286 words
A method of fabricating the capacitors of a DRAM cell, said method comprising the step of: (a) forming MOSFET structures on a silicon substrate, wherein said MOSFET comprises of gate oxide, gate electrode and drain/source regions; (b) continuously forming the first, second, and third dielectric layers overlaying the surface of said silicon substrate; (c) etching said first, second, and third dielectric layer to open a cell contact window for said source region of said MOSFET by conventional lithography and plasma-etching techniques; (d) forming the first polysilicon layer overlaying said third dielectric layer and filling in said cell contact window; (e) anisotropically etching said first polysilicon layer to form the first polysilicon stud therein said cell contact window; (f) removing said third dielectric layer to expose said second dielectric layer and said first polysilicon stud; (g) forming the second polysilicon layer overlaying said second dielectric layer and said first polysilicon stud; (h) forming the fourth dielectric layer overlaying overlaying said second polysilicon layer; (i) anisotropically etching said fourth dielectric layer to form the fourth dielectric spacers on the sidewalls of said first polysilicon stud; (j) forming the third polysilicon layer overlayilng said second dielectric layer, remaining of said second polysilicon layer and said fourth dielectric spacers; (k) vertically anisotropically etching said second and third polysilicon layers thereby leaving the third polysilicon spacers and said second polysilicon layer underneath on the sidewalls of said first polysilicon stud; (l) removing said fourth dielectric spacers, the storage node of said capacitor which is consist of the remaining said first polysilicon stud, said second polysilicon layer, and said third polysilicon spacers is constructed; (m) forming the capacitor dielectric layer and top plate of said capacitor by standard integrated circuit processing procedure.
Claim 2
Independent Claim
286 words
A method of fabricating the capacitors of a DRAM cell, said method comprising the step of: (a) forming MOSFET structures on a silicon substrate, wherein said MOSFET comprises of gate oxide, gate electrode and drain/source regions; (b) continuously forming the first, second, and third dielectric layers overlaying the surface of said silicon substrate; (c) etching said first, second, and third dielectric layer to open a cell contact window for said source region of said MOSFET by conventional lithography and plasma-etching techniques; (d) forming the first polysilicon layer overlaying said third dielectric layer and filling in said cell contact window; (e) anisotropically etching said first polysilicon layer to form the first polysilicon stud therein said cell contact window; (f) removing said third dielectric layer to expose said second dielectric layer and said first polysilicon stud; (g) forming the second polysilicon layer overlaying said second dielectric layer and said first polysilicon stud; (h) forming the fourth dielectric layer overlaying overlaying said second polysilicon layer; (i) anisotropically etching said fourth dielectric layer to form the fourth dielectric spacers on the sidewalls of said first polysilicon stud; (j) forming the third polysilicon layer overlayilng said second dielectric layer, remaining of said second polysilicon layer and said fourth dielectric spacers; (k) vertically anisotropically etching said second and third polysilicon layers thereby leaving the third polysilicon spacers and said second polysilicon layer underneath on the sidewalls of said first polysilicon stud; (l) removing said fourth dielectric spacers, the storage node of said capacitor which is consist of the remaining said first polysilicon stud, said second polysilicon layer, and said third polysilicon spacers is constructed; (m) forming the capacitor dielectric layer and top plate of said capacitor by standard integrated circuit processing procedure.
Claim 3
Dependent Claim
30 words
The method of claim 1, wherein said first dielectric layer is made of borophosphosilicate glass (BPSG) or undoped silicate glass (USG) which has a thickness of 3000 to 8000 Angstroms.
Claim 4
Dependent Claim
28 words
The method of claim 1, wherein said second dielectric layer is formed with low chemical vapor deposition (LPCVD) nitride, which has a thickness of 100 to 1500 Angstroms.
Claim 5
Dependent Claim
27 words
The method of claim 1, wherein said third dielectric layer is formed with silicon dioxide (SiO 2 ), which has a thickness of 1000 to 8000 Angstroms.
Claim 6
Dependent Claim
27 words
The method of claim 1, wherein said fourth dielectric layer is formed with silicon dioxide (SiO 2 ), which has a thickness of 800 to 2400 Angstroms.
Claim 7
Dependent Claim
24 words
The method of claim 1, wherein said first polysilicon layer is formed which has a thickness of 1000 to 4000 Angstroms by LPCVD technique.
Claim 8
Dependent Claim
24 words
The method of claim 1, wherein said second polysilicon layer which has a thickness of 500 to 2000 Angstroms, is formed by LPCVD technique.
Claim 9
Dependent Claim
24 words
The method of claim 1, wherein said third polysilicon layer which has a thickness of 1000 to 2000 Angstroms, is formed by LPCVD technique.
Claim 10
Dependent Claim
37 words
The method of claim 1, wherein said capacitor dielectric layer is made of nitride/oxide (NO) doublelayer or oxide/nitride/oxide (ONO) triplelayer or tantalum oxide (Ta 2 O 5 ), which has a thickness of 20 to 100 Angstroms.
Claim 11
Dependent Claim
25 words
The method of claim 1, wherein said top plate of the capacitor which is formed with polysilicon, has a thickness of 1000 to 2000 Angstroms.
Claim 12
Dependent Claim
29 words
The method of claim 1, wherein said storage node of the capacitor is the same conduction type (N type or P type) as said source/drain regions of a MOSFET.
Claim 13
Independent Claim
263 words
A method of forming polysilicon capacitor structure, said method comprising the steps of: (a) continuously forming the first, second, and third dielectric layers overlaying the surface of said silicon substrate; (b) etching said first, second, and third dielectric layer to open a cell contact window for said source region of said MOSFET by conventional lithography and plasma-etching techniques; (c) forming the first polysilicon layer overlaying said third dielectric layer and filling in said cell contact window; (d) anisotropically etching said first polysilicon layer to form the first polysilicon stud therein said cell contact window; (e) removing said third dielectric layer to expose said second dielectric layer and said first polysilicon stud; (f) forming the second polysilicon layer overlaying said second dielectric layer and said first polysilicon stud; (g) forming the fourth dielectric layer overlaying overlaying said second polysilicon layer; (h) anisotropically etching said fourth dielectric layer to form the fourth dielectric spacers on the sidewalls of said first polysilicon stud; (i) forming the third polysilicon layer overlayilng said second dielectric layer, remaining of said second polysilicon layer and said fourth dielectric spacers; (j) vertically anisotropically etching said second and third polysilicon layers thereby leaving the third polysilicon spacers and said second polysilicon layer underneath on the sidewalls of said first polysilicon stud; (k) removing said fourth dielectric spacers, the storage node of said capacitor which is consist of the remaining said first polysilicon stud, said second polysilicon layer, and said third polysilicon spacers is constructed; (l) forming the capacitor dielectric layer and top plate of said capacitor by standard integrated circuit processing procedure.
Claim 14
Independent Claim
263 words
A method of forming polysilicon capacitor structure, said method comprising the steps of: (a) continuously forming the first, second, and third dielectric layers overlaying the surface of said silicon substrate; (b) etching said first, second, and third dielectric layer to open a cell contact window for said source region of said MOSFET by conventional lithography and plasma-etching techniques; (c) forming the first polysilicon layer overlaying said third dielectric layer and filling in said cell contact window; (d) anisotropically etching said first polysilicon layer to form the first polysilicon stud therein said cell contact window; (e) removing said third dielectric layer to expose said second dielectric layer and said first polysilicon stud; (f) forming the second polysilicon layer overlaying said second dielectric layer and said first polysilicon stud; (g) forming the fourth dielectric layer overlaying overlaying said second polysilicon layer; (h) anisotropically etching said fourth dielectric layer to form the fourth dielectric spacers on the sidewalls of said first polysilicon stud; (i) forming the third polysilicon layer overlayilng said second dielectric layer, remaining of said second polysilicon layer and said fourth dielectric spacers; (j) vertically anisotropically etching said second and third polysilicon layers thereby leaving the third polysilicon spacers and said second polysilicon layer underneath on the sidewalls of said first polysilicon stud; (k) removing said fourth dielectric spacers, the storage node of said capacitor which is consist of the remaining said first polysilicon stud, said second polysilicon layer, and said third polysilicon spacers is constructed; (l) forming the capacitor dielectric layer and top plate of said capacitor by standard integrated circuit processing procedure.
Claim 15
Dependent Claim
30 words
The method of claim 12, wherein said first dielectric layer is made of borophosphosilicate glass (BPSG) or undoped silicate glass (USG) which has a thickness of 3000 to 8000 Angstroms.
Claim 16
Dependent Claim
28 words
The method of claim 12, wherein said second dielectric layer is formed with low chemical vapor deposition (LPCVD) nitride, which has a thickness of 100 to 1500 Angstroms.
Claim 17
Dependent Claim
27 words
The method of claim 12, wherein said third dielectric layer is formed with silicon dioxide (SiO 2 ), which has a thickness of 1000 to 8000 Angstroms.
Claim 18
Dependent Claim
27 words
The method of claim 12, wherein said fourth dielectric layer is formed with silicon dioxide (SiO 2 ), which has a thickness of 800 to 2400 Angstroms.
Claim 19
Dependent Claim
24 words
The method of claim 12, wherein said first polysilicon layer which has a thickness of 1000 to 4000 Angstroms is formed by LPCVD technique.
Claim 20
Dependent Claim
24 words
The method of claim 12, wherein said second polysilicon layer which has a thickness of 500 to 2000 Angstroms, is formed by LPCVD technique.
Claim 21
Dependent Claim
24 words
The method of claim 12, wherein said third polysilicon layer which has a thickness of 1000 to 2000 Angstroms, is formed by LPCVD technique.
Claim 22
Dependent Claim
37 words
The method of claim 12, wherein said capacitor dielectric layer which is made of nitride/oxide (NO) doublelayer or oxide/nitride/oxide (ONO) triplelayer or tantalum oxide (Ta 2 O 5 ), has a thickness of 20 to 100 Angstroms.
Claim 23
Dependent Claim
25 words
The method of claim 12, wherein said top plate of the capacitor which is formed with polysilicon, has a thickness of 1000 to 2000 Angstroms.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-09 | 2001-09-08 | 2002-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-09 | 2005-09-08 | 2006-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-09 | 2009-09-08 | 2010-03-10 | $7700.00 | Window Closed / Lapsed |