Patent US5889293A successfully refreshed from Google Patents.
US5889293A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrical contact to buried SOI structures
Assignee: International Business Machines Corp
•
Filing: 1997-04-04
•
Granted: 1999-03-30
•
Expires: 2017-04-04
Abstract
Abstract Electrically conductive studs are employed to interconnect bulk active devices and SOI devices in a semiconductor device. Also provided is a method for fabricating such devices.
Inventors
- 👤 Matthew J. Rutten
- 👤 Steven H. Voldman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:40
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/021; H10D; H10D86/00; H10D86/01; H10D86/201; H10P; H10P14/00; H10P14/20
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
78 words
A thin film silicon-on-insulator semiconductor device which comprises a silicon substrate having active device regions therein; a buried silicon dioxide insulator layer located above said silicon substrate; an upper silicon layer having active device regions located above said buried silicon dioxide insulator layer; electrically conductive studs that interconnect active region in said silicon substrate to active device regions above said buried silicon dioxide, and insulation that at least partially electrically insulates said studs from said upper silicon layer.
Claim 2
Dependent Claim
78 words
A thin film silicon-on-insulator semiconductor device which comprises a silicon substrate having active device regions therein; a buried silicon dioxide insulator layer located above said silicon substrate; an upper silicon layer having active device regions located above said buried silicon dioxide insulator layer; electrically conductive studs that interconnect active region in said silicon substrate to active device regions above said buried silicon dioxide, and insulation that at least partially electrically insulates said studs from said upper silicon layer.
Claim 3
Dependent Claim
25 words
The silicon-on-insulation semiconductor device of claim 1 which further includes insulation to electrically isolate said studs from the top surface of said upper silicon layer.
Claim 4
Dependent Claim
20 words
The silicon-on-insulator semiconductor device of claim 1 wherein said studs extend to the top surface of said upper silicon layer.
Claim 5
Dependent Claim
86 words
A thin film silicon-on-insulator semiconductor device which comprises a silicon substrate; a buried silicon dioxide insulator layer located above said silicon substrate; and having an electrically conductive region located therein; an upper silicon layer having active device region located above said buried silicon dioxide insulator layer; electrically conductive studs that interconnect electrically conductive region located in said buried silicon dioxide insulator layer to active device regions above said buried silicon dioxide, and insulation that at least partially electrically insulates said studs from said upper silicon layer.
Claim 6
Dependent Claim
86 words
A thin film silicon-on-insulator semiconductor device which comprises a silicon substrate; a buried silicon dioxide insulator layer located above said silicon substrate; and having an electrically conductive region located therein; an upper silicon layer having active device region located above said buried silicon dioxide insulator layer; electrically conductive studs that interconnect electrically conductive region located in said buried silicon dioxide insulator layer to active device regions above said buried silicon dioxide, and insulation that at least partially electrically insulates said studs from said upper silicon layer.
Claim 7
Dependent Claim
25 words
The silicon-on-insulation semiconductor device of claim 4 which further includes insulation to electrically isolate said studs from the top surface of said upper silicon layer.
Claim 8
Dependent Claim
20 words
The silicon-on-insulator semiconductor device of claim 4 wherein said studs extend to the top surface of said upper silicon layer.
Claim 9
Dependent Claim
89 words
A thin film silicon-on-insulator semiconductor device which comprises a silicon substrate having active regions therein; a buried silicon dioxide insulator layer located above said silicon substrate and having an electrically conductive region located therein; an upper silicon layer having active device regions located above said buried silicon dioxide insulator layer; electrically conductive studs that interconnect said electrically conductive region located in said buried silicon dioxide insulator layer to active regions in said silicon substrate; and insulation that at least partially electrically insulated said studs from said upper silicon layer.
Claim 10
Dependent Claim
89 words
A thin film silicon-on-insulator semiconductor device which comprises a silicon substrate having active regions therein; a buried silicon dioxide insulator layer located above said silicon substrate and having an electrically conductive region located therein; an upper silicon layer having active device regions located above said buried silicon dioxide insulator layer; electrically conductive studs that interconnect said electrically conductive region located in said buried silicon dioxide insulator layer to active regions in said silicon substrate; and insulation that at least partially electrically insulated said studs from said upper silicon layer.
Claim 11
Dependent Claim
20 words
The silicon-on-insulator semiconductor device of claim 7 wherein said studs extend to the top surface of said upper silicon layer.
Claim 12
Dependent Claim
20 words
The silicon-on-insulator semiconductor device of claim 7 wherein said studs also interconnect active device regions in said upper silicon layer.
References Cited (Backward Citations)
US3791024A
Cited
US4104086A
Cited
US4256514A
Cited
US4283249A
Cited
US4473598A
Cited
US4505893A
Cited
US4907053A
Cited
US4889829A
Cited
US4989057A
Cited
US5258318A
Cited
US5521401A
Cited
US5371401A
Cited
US5312777A
Cited
US5606186A
Cited
US5612552A
Cited
US5399507A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-29 | 2002-09-28 | 2003-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-29 | 2006-09-28 | 2007-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-29 | 2010-09-28 | 2011-03-30 | $7700.00 | Window Closed / Lapsed |