Semiconductor integrated circuit

Claim 2

A semiconductor integrated circuit comprising an insulated-gate transistor serving as a driving transistor and composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between said source and drain regions, an insulating layer covering the entire surface of said channel region except for portions adjacent to said source and drain regions, said insulating layer having at least a thinner portion, and a gate electrode of a conductive material disposed adjacent the thinner portion of said insulating layer for maintaining said channel region substantially in floating condition, the impurity concentration N of the channel region having a relation of N<D -3 with respect to the depth D of the channel.

Claim 3

A semiconductor integrated circuit of claim 1 wherein said channel region has an opposite conductivity type to that of said source region.

Claim 4

A semiconductor integrated circuit of claim 1 wherein said channel region is formed of a high resistivity region.

Claim 5

A semiconductor integrated circuit of claim 3 wherein an insulating layer is provided for covering the entire surface of the channel region except for the portion adjacent to the source and drain region and wherein said insulating layer covers the gate electrode side face and the channel surface opposed to the gate electrode.

Claim 6

A semiconductor integrated circuit of claim 3 including an insulating layer for covering the entire surface of the channel region except for the portions adjacent to the source and drain regions and wherein said insulating layer covers the periphery of the channel region continuously to the insulating layer of the gate electrode side.

Claim 7

A semiconductor integrated circuit of claim 1 wherein the gate electrode adjacent the insulating layer covering the channel is formed of an opposite conductivity type than the source region.

Claim 8

A semiconductor integrated circuit of claim 1 wherein the gate insulating layer is formed of two layers of a SIO 2 film layer and a Ta 2 O 5 film layer.

Claim 9

A semiconductor integrated circuit comprising an insulated-gate transistor serving as a driving transistor and composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between said source and drain regions, an insulating layer covering the almost entire surface of said channel region except for portions adjacent to said source and drain regions, said insulating layer having at least a thinner portion, and a gate electrode of a conductive material disposed adjacent the thinner portion of said insulating layer for maintaining said channel region substantially in floating condition, the impurity concentration N of the channel region having a relation of N<D -3 with respect to the depth D of the channel.

Claim 10

A semiconductor integrated circuit comprising an insulated-gate transistor serving as a driving transistor and composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between said source and drain regions, an insulating layer covering the almost entire surface of said channel region except for portions adjacent to said source and drain regions, said insulating layer having at least a thinner portion, and a gate electrode of a conductive material disposed adjacent the thinner portion of said insulating layer for maintaining said channel region substantially in floating condition, the impurity concentration N of the channel region having a relation of N<D -3 with respect to the depth D of the channel.

Claim 11

A semiconductor integrated circuit of claim 8 wherein said channel region has an opposite conductivity type to that of said source region.

Claim 12

A semiconductor integrated circuit of claim 9 wherein a very high impurity concentration region of the same conductivity type as said channel region is disposed on a part of the junction surface of said source region and said channel region adjacent the back surface thereof.

Claim 13

A semiconductor integrated circuit of claim 8 wherein said channel region is formed of a high resistivity region.

Claim 14

A semiconductor integrated circuit of claim 11 wherein a very high impurity concentration region of an opposite conductivity type to that of said source region is disposed on a part of the junction surface of said source region and said channel region adjacent the back surface thereof.

Claim 15

A semiconductor integrated circuit of claim 11 wherein an insulating layer is provided for covering the almost entire surface of the channel region except for the portion adjacent to the source and drain regions and wherein said insulating layer covers the gate electrode side face and the channel surface opposed to the gate electrode.

Claim 16

A semiconductor integrated circuit of claim 11 including an insulating layer for covering the almost entire surface of the channel regions except for the portion adjacent to the source and drain region and wherein said insulating layer covers the periphery of the channel region continuously to the insulating layer of the gate electrode side.

Claim 17

A semiconductor integrated circuit of claim 8 wherein the gate electrode adjacent the insulating layer covering the channel is formed of an opposite conductivity type than the source region.

Claim 18

A semiconductor integrated circuit of claim 8 wherein the gate insulating layer is formed of two layers of a SiO 2 film layer and a Ta 2 O 5 film layer.

Claim 19

A semiconductor integrated circuit comprising two complementary insulated-gate transistors of different conductivity types having drain electrodes directly connected to each other and gate electrodes directly connected to each other, the connected gate electrodes serving as an input terminal and the connected drain electrodes serving as an output terminal, each of said insulated-gate transistors being composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between said source and drain regions, an insulating layer covering the entire surface of said channel region except for portions adjacent to said source and drain regions, the insulating layer which covers said channel region having at least a thinner portion, and a gate electrode of a conductive material disposed adjacent to the thinner portion of said insulating layer for maintaining said channel region substantially in floating condition, the impurity concentration N of the channel region having a relation of N<D -3 with respect to the depth D of the channel.

Claim 20

A semiconductor integrated circuit comprising two complementary insulated-gate transistors of different conductivity types having drain electrodes directly connected to each other and gate electrodes directly connected to each other, the connected gate electrodes serving as an input terminal and the connected drain electrodes serving as an output terminal, each of said insulated-gate transistors being composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between said source and drain regions, an insulating layer covering the entire surface of said channel region except for portions adjacent to said source and drain regions, the insulating layer which covers said channel region having at least a thinner portion, and a gate electrode of a conductive material disposed adjacent to the thinner portion of said insulating layer for maintaining said channel region substantially in floating condition, the impurity concentration N of the channel region having a relation of N<D -3 with respect to the depth D of the channel.

Claim 21

A semiconductor integrated circuit of claim 17 wherein said channel region has an opposite conductivity type to that of said source region.

Claim 22

A semiconductor integrated circuit of claim 17 wherein said channel region is formed of a high resistivity region.

Claim 23

A semiconductor integrated circuit of claim 19 wherein an insulating layer is provided for covering the entire surface of the channel region except for the portions adjacent to the source and drain regions and wherein said insulating layer covers the gate electrode side face and the channel surface opposed to the gate electrode.

Claim 24

A semiconductor integrated circuit of claim 19 including an insulating layer for covering the entire surface of the channel region except for the portions adjacent to the source and drain regions and wherein said insulating layer covers the periphery of the channel region continuously to the insulating layer of the gate electrode side.

Claim 25

A semiconductor integrated circuit of claim 17 wherein the gate electrode adjacent the insulating layer covering the channel is formed of an opposite conductivity type than the source region.

Claim 26

A semiconductor integrated circuit of claim 17 wherein the gate insulating layer is formed of two layers of a SiO 2 film layer and a Ta 2 O 5 film layer.

Claim 27

A semiconductor integrated circuit comprising two complementary insulated-gate transistors of different conductivity types having drain electrodes directly connected to each other and gate electrodes directly connected to each other, the connected gate electrodes serving as an input terminal and the connected drain electrodes serving as an output terminal, each of said insulated-gate transistors being composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between said source and drain regions, an insulating layer covering the almost entire surface of said channel region except for portions adjacent to said source and drain regions, the insulating layer which covers said channel region having at least a thinner portion, and a gate electrode of a conductive material disposed adjacent to the thinner portion of said insulating layer for maintaining said channel region substantially in floating condition, the impurity concentration N of the channel region having a relation of N<D -3 with respect to the depth D of the channel.

Claim 28

A semiconductor integrated circuit comprising two complementary insulated-gate transistors of different conductivity types having drain electrodes directly connected to each other and gate electrodes directly connected to each other, the connected gate electrodes serving as an input terminal and the connected drain electrodes serving as an output terminal, each of said insulated-gate transistors being composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between said source and drain regions, an insulating layer covering the almost entire surface of said channel region except for portions adjacent to said source and drain regions, the insulating layer which covers said channel region having at least a thinner portion, and a gate electrode of a conductive material disposed adjacent to the thinner portion of said insulating layer for maintaining said channel region substantially in floating condition, the impurity concentration N of the channel region having a relation of N<D -3 with respect to the depth D of the channel.

Claim 29

A semiconductor integrated circuit of claim 24 wherein said channel region has an opposite conductivity type to that of said source region.

Claim 30

A semiconductor integrated circuit of claim 25 wherein a very high impurity concentration region of the same conductivity type as said channel region is disposed on a part of the junction surface of said source region and said channel region adjacent the back surface thereof.

Claim 31

A semiconductor integrated circuit of claim 24 wherein said channel region is formed of a high resistivity region.

Claim 32

A semiconductor integrated circuit of claim 27 wherein a very high impurity concentration region of an opposite conductivity type to that of said source region is disposed on a part of the junction surface of said source region and said channel region adjacent the back surface thereof.

Claim 33

A semiconductor integrated circuit of claim 27 wherein an insulating layer is provided for covering the almost entire surface of the channel region except for the portions adjacent to the source and drain regions and wherein said insulating layer covers the gate electrode side face and the surface opposed to the gate electrode.

Claim 34

A semiconductor integrated circuit of claim 27 including an insulating layer for covering the almost entire surface of the channel region except for the portions adjacent to the source and drain regions and wherein said insulating layer covers the periphery of the channel region continuously to the insulating layer of the gate electrode side.

Claim 35

A semiconductor integrated circuit of claim 24 wherein the gate electrode adjacent the insulating layer covering the channel is formed of an opposite conductivity type than the source region.

Claim 36

A semiconductor integrated circuit of claim 24 wherein the gate insulating layer is formed of two layers of an SiO 2 film layer and a Ta 2 O 5 film layer.

Claim 37

A semiconductor integrated circuit comprising an insulated-gate transistor serving as a driving transistor and composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between said source and drain regions, an insulating layer covering the entire surface of said channel region except for portions adjacent to said source and drain regions, said insulating layer having at least two thinner portions, and at least two gate electrodes of a conductive material disposed adjacent these thinner portions of said insulating layer for maintaining said channel region substantially in floating condition.

Claim 38

A semiconductor integrated circuit comprising an insulated-gate transistor serving as a driving transistor and composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between said source and drain regions, an insulating layer covering the entire surface of said channel region except for portions adjacent to said source and drain regions, said insulating layer having at least two thinner portions, and at least two gate electrodes of a conductive material disposed adjacent these thinner portions of said insulating layer for maintaining said channel region substantially in floating condition.

Claim 39

A semiconductor integrated circuit of claim 33 wherein the impurity concentration N of the channel region has a relation of N<D -3 with respect to the depth D of the channel.

Claim 40

A semiconductor integrated circuit comprising two complementary insulated-gate transistors of different conductivity types having drain electrodes directly connected to each other and gate electrodes directly connected to each other, the connected gate electrodes serving as an input terminal and the connected drain electrodes serving as an output terminal, each of said insulated-gate transistors being composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between said source and drain regions, an insulating layer covering the entire surface of said channel region except for portions adjacent to said source and drain regions, the insulating layer which covers said channel region having at least two thinner portions, and at least two gate electrodes of a conductive material disposed adjacent to these thinner portions of said insulating layer for maintaining said channel region substantially in floating condition.

Claim 41

A semiconductor integrated circuit comprising two complementary insulated-gate transistors of different conductivity types having drain electrodes directly connected to each other and gate electrodes directly connected to each other, the connected gate electrodes serving as an input terminal and the connected drain electrodes serving as an output terminal, each of said insulated-gate transistors being composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between said source and drain regions, an insulating layer covering the entire surface of said channel region except for portions adjacent to said source and drain regions, the insulating layer which covers said channel region having at least two thinner portions, and at least two gate electrodes of a conductive material disposed adjacent to these thinner portions of said insulating layer for maintaining said channel region substantially in floating condition.

Claim 42

A semiconductor integrated circuit of claim 35 wherein the impurity concentration N of the channel region has a relation of N<D -3 with respect to the depth D of the channel.