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US5885861A
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Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor
Assignee: GlobalFoundries Inc
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Filing: 1997-05-30
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Granted: 1999-03-23
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Expires: 2017-05-30
Abstract
Abstract Diffusion of dopants within the gate of the transistor and/or the source/drain regions can be inhibited by the ion co-implantation of impurities in addition to the ion implantation of the n-type or p-type dopants. Implanting a combination of nitrogen and carbon for p-type devices in addition to the p-type dopants and implanting a combination of nitrogen and fluorine for n-type devices in addition to the n-type dopants, significantly reduces the diffusion of the n-type and p-type dopants. The co-implantation of the additional impurities may be performed before patterning of the polysilicon layer to yield the gate conductors. The impurities may be implanted first, followed by the n-type or p-type dopants. Additional implantation of the impurities may be performed after the patterning of the polysilicon layer in order to reduce dopant diffusion in the source and drain regions. The ion implantation of the gate conductors and source/drain regions may performed at the same time following the patterning of the polysilicon layer.
Inventors
- 👤 Mark I. Gardner
- 👤 H. Jim Fulford
- 👤 Derrick J. Wristers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:17
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01332; H10D64/01336; H10D64/01338; H10D64/0134; H10D64/60; H10D64/66; H10D64/661; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/0172; H10D84/02; H10D84/03; H10D84/038; H10D64/01346; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10P30/208; Y; Y10; Y10S; Y10S257/00; Y10S257/914; Y10S438/00; Y10S438/914; Y10S438/918
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
193 words
A method for fabricating an integrated circuit comprising: providing a semiconductor substrate, wherein said semiconductor comprises an NMOS region and a PMOS region and wherein said NMOS region and said PMOS region are laterally disposed on either side of an isolation structure; forming a gate dielectric on an upper surface of said semiconductor substrate; forming an NMOS gate conductor in said NMOS region and a PMOS gate conductor in said PMOS region, wherein said NMOS and said PMOS gate conductors are formed above said gate dielectric; introducing nitrogen into said NMOS gate conductor and into said PMOS conductor; introducing fluorine into said NMOS gate conductor while said PMOS region is completely masked; introducing an n-type dopant into said NMOS gate conductor while said PMOS region is completely masked; introducing carbon into said PMOS gate conductor while said NMOS region is completely masked; introducing a p-type dopant into said PMOS gate conductor while said NMOS region is completely masked; introducing an n-type dopant into said NMOS region of said semiconductor substrate to form NMOS source/drain regions; and introducing a p-type dopant into said PMOS region of said semiconductor substrate to form PMOS source/drain regions.
Claim 2
Independent Claim
193 words
A method for fabricating an integrated circuit comprising: providing a semiconductor substrate, wherein said semiconductor comprises an NMOS region and a PMOS region and wherein said NMOS region and said PMOS region are laterally disposed on either side of an isolation structure; forming a gate dielectric on an upper surface of said semiconductor substrate; forming an NMOS gate conductor in said NMOS region and a PMOS gate conductor in said PMOS region, wherein said NMOS and said PMOS gate conductors are formed above said gate dielectric; introducing nitrogen into said NMOS gate conductor and into said PMOS conductor; introducing fluorine into said NMOS gate conductor while said PMOS region is completely masked; introducing an n-type dopant into said NMOS gate conductor while said PMOS region is completely masked; introducing carbon into said PMOS gate conductor while said NMOS region is completely masked; introducing a p-type dopant into said PMOS gate conductor while said NMOS region is completely masked; introducing an n-type dopant into said NMOS region of said semiconductor substrate to form NMOS source/drain regions; and introducing a p-type dopant into said PMOS region of said semiconductor substrate to form PMOS source/drain regions.
Claim 3
Dependent Claim
74 words
The method as recited in claim 1, further comprising, prior to introducing said n-type dopant into said NMOS source/drain regions and prior to introducing said p-type dopant into said PMOS source/drain regions: introducing nitrogen into said NMOS source/drain regions and into said PMOS source/drain regions; introducing fluorine into said NMOS source/drain regions while said PMOS region is completely masked and introducing carbon into said PMOS source/drain regions while said NMOS region is completely masked.
Claim 4
Dependent Claim
19 words
The method as recited in claim 1, wherein said semiconductor substrate comprises a doped epitaxy layer of single-crystalline silicon.
Claim 5
Dependent Claim
33 words
The method as recited in claim 1, wherein said isolation structure comprises: a trench void created by etching said semiconductor substrate; and a TEOS based oxide deposited by CVD into said trench void.
Claim 6
Dependent Claim
28 words
The method as recited in claim 1, wherein the step of forming said gate dielectric comprises thermally oxidizing said semiconductor substrate to a thickness of approximately 15-50 Å.
Claim 7
Dependent Claim
23 words
The method as recited in claim 5, wherein the step of forming said gate dielectric is performed in a rapid thermal anneal apparatus.
Claim 8
Dependent Claim
20 words
The method as recited in claim 1, wherein said NMOS gate conductor and said PMOS gate conductor comprise polycrystalline silicon.
Claim 9
Dependent Claim
25 words
The method as recited in claim 1, wherein the steps of introducing nitrogen, fluorine, carbon, n-type dopants, and p-type dopants comprises introduction with ion implantation.
Claim 10
Dependent Claim
16 words
The method as recited in claim 1, wherein said n-type dopants comprise phosphorus or arsenic impurities.
Claim 11
Dependent Claim
14 words
The method as recited in claim 1, wherein said p-type dopants comprise boron impurities.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-22 | 2002-09-21 | 2003-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-22 | 2006-09-21 | 2007-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-22 | 2010-09-21 | 2011-03-23 | $7700.00 | Window Closed / Lapsed |