Patent US5879983A successfully refreshed from Google Patents.
US5879983A
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Semiconductor device and method for manufacturing the same
Assignee: RPX Corp
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Filing: 1996-09-18
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Granted: 1999-03-09
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Expires: 2016-09-18
Abstract
Abstract A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled. In the semiconductor device in which a transistor, a capacitive element, a resistive film and the like are provided, the occupied area can be reduced and the manufacturing cost can be cut down.
Inventors
- 👤 Mizuki Segawa
- 👤 Toshiki Yabu
- 👤 Takashi Uehara
- 👤 Takashi Nakabayashi
- 👤 Kyoji Yamashita
- 👤 Takaaki Ukeda
- 👤 Masatoshi Arai
- 👤 Takayuki Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:25
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/43; H10B41/48; H10D; H10D1/00; H10D1/60; H10D1/68; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D84/014; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/811; H10D84/813; H10D84/817; Y; Y10; Y10S; Y10S438/00; Y10S438/957
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
272 words
A method for manufacturing a semiconductor device in which a capacitive element is provided on a semiconductor substrate, comprising the steps of: depositing a first conductor film on the semiconductor substrate intervened by an insulating member; depositing an insulating film on the first conductor film; patterning the insulating film to form a capacitive film of the capacitive element; depositing a second conductor film on the insulating film and the first conductor film; and patterning the first and second conductor films by using an etching mask including at least a part of the capacitive film to form an upper capacitive electrode of the capacitive element by the second conductor film and to form a lower capacitive electrode of the capacitive element by the first conductor film, wherein the step of forming the upper capacitive electrode and the lower capacitive electrode is performed by using, as etching masks, the capacitive film and a resist film having at least two regions of first and second regions, the first region covering a part of the capacitive film and the second region covering a region from an end of the capacitive film to the outside of the capacitive film, to form the upper capacitive electrode made of the second conductor film which is left in a lower portion of the first region, a leading electrode of the lower capacitive electrode made of the second conductor film which is left in a lower portion of the second region, and the lower capacitive electrode made of the first conductor film which is left over a region covered with at least one of the capacitive film and the resist film.
Claim 2
Independent Claim
272 words
A method for manufacturing a semiconductor device in which a capacitive element is provided on a semiconductor substrate, comprising the steps of: depositing a first conductor film on the semiconductor substrate intervened by an insulating member; depositing an insulating film on the first conductor film; patterning the insulating film to form a capacitive film of the capacitive element; depositing a second conductor film on the insulating film and the first conductor film; and patterning the first and second conductor films by using an etching mask including at least a part of the capacitive film to form an upper capacitive electrode of the capacitive element by the second conductor film and to form a lower capacitive electrode of the capacitive element by the first conductor film, wherein the step of forming the upper capacitive electrode and the lower capacitive electrode is performed by using, as etching masks, the capacitive film and a resist film having at least two regions of first and second regions, the first region covering a part of the capacitive film and the second region covering a region from an end of the capacitive film to the outside of the capacitive film, to form the upper capacitive electrode made of the second conductor film which is left in a lower portion of the first region, a leading electrode of the lower capacitive electrode made of the second conductor film which is left in a lower portion of the second region, and the lower capacitive electrode made of the first conductor film which is left over a region covered with at least one of the capacitive film and the resist film.
Claim 3
Dependent Claim
130 words
The method for manufacturing a semiconductor device of claim 1, further comprising the step of forming a gate insulating film in an active region of the semiconductor substrate prior to the step of depositing a first conductor film, wherein the first conductor film is deposited also on the gate insulating film at the step of depositing a first conductor film, the insulating film in the active region is removed at the step of patterning an insulating film, the second conductor film is laminated on the first conductor film in the active region at the step of depositing a second conductor film, and a gate electrode made of the first and second conductor films is formed in the active region at the step of patterning the first and second conductor films.
Claim 4
Dependent Claim
163 words
The method for manufacturing a semiconductor device of claim 2, wherein a part of the insulating film in a part of the active region is left as an insulating film on a floating gate of an EEPROM at the step of patterning an insulating film, the second conductor film is laminated on the first conductor film and the insulating film on the floating gate in the part of the active region at the step of depositing a second conductor film, and a control gate electrode of the EEPROM made of the second conductor film which is left below the resist film is formed by using the resist film which covers a part of the insulating film on the floating gate and a floating gate electrode of the EEPROM made of the first conductor film which is left below the insulating film on the floating gate in the part of the active region at the step of patterning the first and second conductor films.
Claim 5
Dependent Claim
91 words
The method for manufacturing a semiconductor device of claim 1, further comprising, prior to the step of patterning the insulating film, the steps of: forming an element isolating trench by sequentially removing the insulating film, the first conductor film and the semiconductor substrate in a region where an element isolation is to be formed; depositing an insulating film for the element isolation which fills in the element isolating trench and covers the insulating film; and planarizing the insulating film for the element isolation by using the insulating film as a mask.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-08 | 2002-09-07 | 2003-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-08 | 2006-09-07 | 2007-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-08 | 2010-09-07 | 2011-03-09 | $7700.00 | Window Closed / Lapsed |