Method for manufacturing a stacked/trench DRAM capacitor

Claim 1

A method for manufacturing a DRAM capacitor, said method being performed on a substrate having a field oxide and a transistor including a gate electrode and source/drain areas formed thereon, said method comprising the steps of: depositing an insulator over the gate electrode and the source/drain areas; depositing a first barrier layer over the insulator; sequentially depositing a first conductive layer and a second barrier layer over the previously applied first barrier layer; etching away portions of the insulator, the first barrier layer, the first conductive layer and the second barrier layer overlying the source/drain areas and spaced from the field oxide to form trenches extending to the source/drain areas; patterning a first layer of resist on the second barrier layer to define a region of the first conductive layer that is to be retained; thereafter etching away portions of the second barrier layer and the first conductive layer not covered by the resist layer; removing the first layer of resist so that a top surface remains; depositing a layer of polysilicon over the top surface, doping an n-type dopant into said polysilicon layer and diffusing said dopant into said substrate to form n + -type diffused regions; patterning a second layer of resist on said polysilicon layer to define a portion of the polysilicon layer that is to be retained; etching the polysilicon layer not covered by the second layer of resist to form a second conductive layer; isotropically etching away said first and second barrier layers so that said first conductive layer, said second conductive layer and said poly spacers are shorted together and thereby form a bottom plate of the DRAM capacitor having a bottom plate surface; depositing a dielectric film on the bottom plate surface; depositing a third conductive layer on the bottom plate surface; patterning a third layer of resist over a portion of the third conductive layer; and etching away a portion of the third conductive layer not covered by the third layer of resist to thereby form a top plate of the DRAM capacitor.

Claim 2

A method for manufacturing a DRAM capacitor, said method being performed on a substrate having a field oxide and a transistor including a gate electrode and source/drain areas formed thereon, said method comprising the steps of: depositing an insulator over the gate electrode and the source/drain areas; depositing a first barrier layer over the insulator; sequentially depositing a first conductive layer and a second barrier layer over the previously applied first barrier layer; etching away portions of the insulator, the first barrier layer, the first conductive layer and the second barrier layer overlying the source/drain areas and spaced from the field oxide to form trenches extending to the source/drain areas; patterning a first layer of resist on the second barrier layer to define a region of the first conductive layer that is to be retained; thereafter etching away portions of the second barrier layer and the first conductive layer not covered by the resist layer; removing the first layer of resist so that a top surface remains; depositing a layer of polysilicon over the top surface, doping an n-type dopant into said polysilicon layer and diffusing said dopant into said substrate to form n + -type diffused regions; patterning a second layer of resist on said polysilicon layer to define a portion of the polysilicon layer that is to be retained; etching the polysilicon layer not covered by the second layer of resist to form a second conductive layer; isotropically etching away said first and second barrier layers so that said first conductive layer, said second conductive layer and said poly spacers are shorted together and thereby form a bottom plate of the DRAM capacitor having a bottom plate surface; depositing a dielectric film on the bottom plate surface; depositing a third conductive layer on the bottom plate surface; patterning a third layer of resist over a portion of the third conductive layer; and etching away a portion of the third conductive layer not covered by the third layer of resist to thereby form a top plate of the DRAM capacitor.

Claim 11

A method for manufacturing a DRAM capacitor on a substrate having a field oxide and a transistor including a gate electrode and source/drain areas formed thereon, the method comprising the steps of: depositing on the substrate an insulator over the gate electrode and source/drain areas; depositing a first barrier layer over the insulator; sequentially depositing a first conductive layer and a second barrier layer over the first barrier layer; removing portions of the insulator, the first barrier layer, the first conductive layer and the second barrier layer above the source/drain areas and forming trenches reaching the source/drain areas adjacent the field oxide; patterning a first layer of resist on the second barrier layer; etching away portions of the second barrier layer and the first conductive layer not covered by the first resist layer; removing what remains of the first layer of resist to define a top surface; depositing a conductive material layer over the top surface, doping an n-type dopant into said conductive material layer, diffusing said dopant into said substrate to form n + -type diffused regions, and shaping the conductive material layer to form spaced-apart poly spacers and poly fins; etching away the first barrier layer and said second barrier layer to thereby form a bottom plate of the DRAM capacitor having a bottom plate surface and defined by the first conductive layer, the poly spacers, and the poly fins; depositing a dielectric film on the bottom plate surface; depositing another conductive layer over the dielectric film; patterning a second layer of resist over a portion of the another conductive layer; and etching away a portion of the another conductive layer not covered by the second layer of resist so that the another conductive layer forms a top plate of the DRAM capacitor.

Claim 12

A method for manufacturing a DRAM capacitor on a substrate having a field oxide and a transistor including a gate electrode and source/drain areas formed thereon, the method comprising the steps of: depositing on the substrate an insulator over the gate electrode and source/drain areas; depositing a first barrier layer over the insulator; sequentially depositing a first conductive layer and a second barrier layer over the first barrier layer; removing portions of the insulator, the first barrier layer, the first conductive layer and the second barrier layer above the source/drain areas and forming trenches reaching the source/drain areas adjacent the field oxide; patterning a first layer of resist on the second barrier layer; etching away portions of the second barrier layer and the first conductive layer not covered by the first resist layer; removing what remains of the first layer of resist to define a top surface; depositing a conductive material layer over the top surface, doping an n-type dopant into said conductive material layer, diffusing said dopant into said substrate to form n + -type diffused regions, and shaping the conductive material layer to form spaced-apart poly spacers and poly fins; etching away the first barrier layer and said second barrier layer to thereby form a bottom plate of the DRAM capacitor having a bottom plate surface and defined by the first conductive layer, the poly spacers, and the poly fins; depositing a dielectric film on the bottom plate surface; depositing another conductive layer over the dielectric film; patterning a second layer of resist over a portion of the another conductive layer; and etching away a portion of the another conductive layer not covered by the second layer of resist so that the another conductive layer forms a top plate of the DRAM capacitor.

Claim 13

A method for manufacturing a DRAM capacitor on a substrate having a field oxide and a transistor including a gate electrode and source/drain areas formed thereon, the method comprising the steps of: depositing on the substrate a layer stack comprising an insulator, a first barrier layer, a first conductive layer, and a second barrier layer over the gate electrode and source/drain areas; removing portions of the layer stack above the source/drain areas and forming trenches reaching the source/drain areas adjacent the field oxide; etching away portions of the second barrier layer and the first conductive layer; depositing a conductive material layer over what remains of the layer stack, doping an n-type dopant into the conductive material layer, diffusing the dopant into the substrate to form n + -type diffused regions, and shaping the conductive material layer to form spaced-apart poly spacers and poly fins; removing the first barrier layer and the second barrier layer to thereby form a bottom plate of the DRAM capacitor having a bottom plate surface and defined by the first conductive layer, the poly spacers, and the poly fins; depositing a dielectric film on the bottom plate surface; and depositing another conductive layer over the dielectric film so that the another conductive layer forms a top plate of the DRAM capacitor.

Claim 14

A method for manufacturing a DRAM capacitor on a substrate having a field oxide and a transistor including a gate electrode and source/drain areas formed thereon, the method comprising the steps of: depositing on the substrate a layer stack comprising an insulator, a first barrier layer, a first conductive layer, and a second barrier layer over the gate electrode and source/drain areas; removing portions of the layer stack above the source/drain areas and forming trenches reaching the source/drain areas adjacent the field oxide; etching away portions of the second barrier layer and the first conductive layer; depositing a conductive material layer over what remains of the layer stack, doping an n-type dopant into the conductive material layer, diffusing the dopant into the substrate to form n + -type diffused regions, and shaping the conductive material layer to form spaced-apart poly spacers and poly fins; removing the first barrier layer and the second barrier layer to thereby form a bottom plate of the DRAM capacitor having a bottom plate surface and defined by the first conductive layer, the poly spacers, and the poly fins; depositing a dielectric film on the bottom plate surface; and depositing another conductive layer over the dielectric film so that the another conductive layer forms a top plate of the DRAM capacitor.