Dynamic random access memory cell having a stacked-trench capacitor that is resistant to alpha particle generated soft errors, and method of manufacturing same

Claim 1

A process for fabricating an array of stacked-trench DRAM cells on a silicon substrate, said substrate having been subjected to both implantation and LOCOS steps to create active areas and field oxide regions thereon, said process comprising the following sequence of steps: (a) patterning wordlines from a first conductive layer overlaid with a layer of silicon dioxide; (b) subjecting the in-process array to an unmasked anti-punchthrough implant; (c) depositing a conformal silicon dioxide spacer layer over the incomplete array; (d) performing an unmasked, lightly-doped source/drain implant aligned to vertical portions of said silicon dioxide spacer layer; (e) depositing a conformal dielectric material external spacer layer over the incomplete array, said external spacer layer being selectively etchable with respect to silicon dioxide; (f) subjecting the in-process array to an anisotropic reactive ion etch in order to create external spacers from said external spacer layer, said external spacers being adjacent said vertical portions of said conformal silicon dioxide spacer layer; (g) performing an unmasked, heavily-doped source/drain implant aligned to the exposed vertical edges of said external spacers; (h) depositing a silicon dioxide etch stop layer; (i) masking the in-process array with photoresist so as to expose storage-node junction regions; (j) etching away portions of said etch stop layer that are within said storage-node junction regions; (k) performing an anisotropic reactive ion etch so as to create trenches in the substrate, each trench being self-aligned to the exposed vertical edges of external spacers on adjacent wordlines; (l) oxidizing exposed substrate regions in order to create a silicon dioxide liner layer within each trench; (m) performing a wet etch to remove external spacers which are adjacent each trench; (n) depositing a conformal storage-node plate layer; (o) creating individual storage-node plates from said conformal storage-node plate layer; (p) depositing a conformal capacitive dielectric layer; and (q) depositing a cell plate layer.