US5869979A
Expired / Lapsed
US
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Technique for preconditioning I/Os during reconfiguration
Assignee: Altera Corp
•
Filing: 1996-05-09
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Granted: 1999-02-09
•
Expires: 2016-05-09
Abstract
Abstract A technique for configuring programmable integrated circuits. The technique involves preconditioning or predefining the outputs and I/Os of a programmable integrated circuit before the device is programmed or reconfigured. When the device is programmed, the outputs and I/Os of the programmable integrated circuit will be driven to the preconditioned or predefined states. The technique may be implemented in conformance with the IEEE 1149.1 boundary scan architecture standard. Standard IEEE 1149.1 instructions may be used. The technique may also be used during in-system programming of programmable integrated circuits.
Inventors
- 👤 Vincent T. Bocchino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:11
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17772; H03K19/17736; H03K19/17744
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
101 words
A method for reconfiguring a programmable integrated circuit comprising: providing a user-selected input to the programmable integrated circuit; driving a pad with the user-selected input when the programmable integrated circuit is being reconfigured, wherein the user-selected input is coupled to a first input of a multiplexer and a data path signal is coupled to a second input of the multiplexer, wherein an output of the multiplexer is coupled to the pad and a control node of the multiplexer is coupled to be controlled by a signal indicating whether the programmable integrated circuit is being reconfigured; and reconfiguring the programmable integrated circuit.
Claim 2
Independent Claim
101 words
A method for reconfiguring a programmable integrated circuit comprising: providing a user-selected input to the programmable integrated circuit; driving a pad with the user-selected input when the programmable integrated circuit is being reconfigured, wherein the user-selected input is coupled to a first input of a multiplexer and a data path signal is coupled to a second input of the multiplexer, wherein an output of the multiplexer is coupled to the pad and a control node of the multiplexer is coupled to be controlled by a signal indicating whether the programmable integrated circuit is being reconfigured; and reconfiguring the programmable integrated circuit.
Claim 3
Dependent Claim
15 words
The method of claim 1 wherein the user-selected input is driven through a tristate buffer.
Claim 4
Dependent Claim
17 words
The method of claim 1 wherein the programmable integrated circuit is reconfigured while on a circuit board.
Claim 5
Dependent Claim
18 words
The method of claim 1 wherein providing a user-selected input comprises storing the user-selected input into a register.
Claim 6
Dependent Claim
17 words
The method of claim 1 wherein the user-selected input is shifted serially into the programmable integrated circuit.
Claim 7
Dependent Claim
16 words
The method of claim 1 wherein the multiplexer is part of a JTAG boundary scan cell.
Claim 8
Dependent Claim
20 words
The method of claim 1 wherein driving a pad with the user-selected input comprises using an IEEE standard 1149.1 instruction.
Claim 9
Independent Claim
136 words
A method of reconfiguring a programmable integrated circuit comprising: transferring a first signal stored in a first register from the first register to a third register in response to an update signal; transferring a second signal stored in a second register from the second register to a fourth register in response to the update signal; controlling a control node of a tristate buffer with the second signal from the fourth register when the programmable integrated circuit is in a reconfigure mode; and transferring the first signal to the tristate buffer when the programmable integrated circuit is in the reconfigure mode, wherein the first signal is driven through the tristate buffer to a pad when the second signal enables the tristate buffer, and the pad is in a high-impedance state when the second signal-disables the tristate buffer.
Claim 10
Independent Claim
136 words
A method of reconfiguring a programmable integrated circuit comprising: transferring a first signal stored in a first register from the first register to a third register in response to an update signal; transferring a second signal stored in a second register from the second register to a fourth register in response to the update signal; controlling a control node of a tristate buffer with the second signal from the fourth register when the programmable integrated circuit is in a reconfigure mode; and transferring the first signal to the tristate buffer when the programmable integrated circuit is in the reconfigure mode, wherein the first signal is driven through the tristate buffer to a pad when the second signal enables the tristate buffer, and the pad is in a high-impedance state when the second signal-disables the tristate buffer.
Claim 11
Dependent Claim
48 words
The method of claim 8 further comprising: in response to a shift signal, linking an output of the first register to an input of the second register; shifting the second signal through the first register into the second register; and shifting the first signal into the first register.
Claim 12
Dependent Claim
23 words
The method of claim 8 further comprising: initializing the first register and the second register by clearing the first register and second register.
Claim 13
Dependent Claim
35 words
The method of claim 8 wherein during controlling a control node of a tristate buffer, a multiplexer decouples a data path input from the tristate buffer and couples the first signal to the tristate buffer.
Claim 14
Dependent Claim
39 words
The method of claim 8 wherein during controlling a control node of a tristate buffer, a multiplexer decouples a tristate path input from the tristate buffer and couples the second signal to the control node of the tristate buffer.
Claim 15
Dependent Claim
22 words
The method of claim 8 further comprising: programming the programmable integrated circuit when the programmable integrated circuit is in the reconfigure mode.
Claim 16
Dependent Claim
24 words
The method of claim 8 wherein the first register, second register, third register, and fourth register are part of a JTAG boundary scan cell.
Claim 17
Dependent Claim
20 words
The method of claim 8 wherein transferring the first signal the tristate buffer comprises using an IEEE standard 1149.1 instruction.
Claim 18
Dependent Claim
134 words
A circuit apparatus for a programmable integrated circuit comprising: a pad; a tristate buffer, coupled to the pad; a first multiplexer, coupled through the tristate buffer to the pad, wherein the first multiplexer selects between a data path input and a user-selected data path input; a second multiplexer, coupled to a control node of the tristate buffer, wherein the second multiplexer selects between a tristate path input and a user-selected tristate path input; and a reconfiguration signal, coupled to the first multiplexer and the second multiplexer, for indicating when the programmable integrated circuit is in a reconfigure mode, wherein during the reconfigure mode, the first multiplexer couples the user-selected data path input to the tristate buffer and the second multiplexer couples the user-selected tristate path input to the control node of the tristate buffer.
Claim 19
Dependent Claim
134 words
A circuit apparatus for a programmable integrated circuit comprising: a pad; a tristate buffer, coupled to the pad; a first multiplexer, coupled through the tristate buffer to the pad, wherein the first multiplexer selects between a data path input and a user-selected data path input; a second multiplexer, coupled to a control node of the tristate buffer, wherein the second multiplexer selects between a tristate path input and a user-selected tristate path input; and a reconfiguration signal, coupled to the first multiplexer and the second multiplexer, for indicating when the programmable integrated circuit is in a reconfigure mode, wherein during the reconfigure mode, the first multiplexer couples the user-selected data path input to the tristate buffer and the second multiplexer couples the user-selected tristate path input to the control node of the tristate buffer.
Claim 20
Dependent Claim
28 words
The circuit of claim 16 further comprising: a first register, coupled to the user-selected data path input; and a second register, coupled to the user-selected tristate path input.
Claim 21
Dependent Claim
40 words
The circuit of claim 16 further comprising: a third register, coupled to the first register, wherein the third register provides a clear function; and a fourth register, coupled to the second register, wherein the fourth register provides a clear function.
Claim 22
Dependent Claim
23 words
The circuit of claim 16 wherein the data path input may be programmably coupled to the global interconnect of the programmable integrated circuit.
Claim 23
Dependent Claim
12 words
A system comprising a programmable integrated circuit as recited in claim 18.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-08 | 2002-08-10 | 2003-02-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-08 | 2006-08-10 | 2007-02-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-08 | 2010-08-10 | 2011-02-09 | $7700.00 | Window Closed / Lapsed |