Patent US2695122A successfully refreshed from Google Patents.
Patent US5864738A successfully refreshed from Google Patents.
US5864738A
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US
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Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller
Assignee: Morgan Stanley and Co LLC
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Filing: 1996-03-13
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Granted: 1999-01-26
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Expires: 2016-03-13
Abstract
Abstract A system and method of transferring information between a peripheral device and an MPP system having an interconnect network and a plurality of processing nodes. Each processing element includes a processor, local memory and a router circuit connected to the interconnect network, the processor and the local memory. Each router circuit includes means for transferring data between the processor and the interconnect network and means for transferring data between the local memory and the interconnect network. An I/O controller is connected to a plurality of the router circuits. Data is then read from the peripheral device and transferred through the I/O controller to local memory of one of the processing elements.
Inventors
- 👤 Richard E. Kessler
- 👤 Steven M. Oberlin
- 👤 Steven L. Scott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:51
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17356; G06F15/17368; G06F15/17375; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817; G06F15/76; G06F15/80; G06F15/8007
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
139 words
A massively parallel processing system, comprising: an interconnect network; a plurality of processing nodes, wherein each processing node includes: a processor; local memory; and a router circuit connected to the interconnect network, the processor and the local memory, wherein the router circuit includes first and second data paths, wherein the router circuit transfers data between the processor and the interconnect network and between the local memory and the interconnect network over said first data path; and a plurality of I/O controllers, including a first I/O controller, wherein each I/O controller is connected to the second data path of a plurality of the router circuits and wherein each router circuit further includes I/O routing means for transferring data between the I/O controller to which the router circuit is connected and local memory of any of the plurality of processing nodes.
Claim 2
Dependent Claim
139 words
A massively parallel processing system, comprising: an interconnect network; a plurality of processing nodes, wherein each processing node includes: a processor; local memory; and a router circuit connected to the interconnect network, the processor and the local memory, wherein the router circuit includes first and second data paths, wherein the router circuit transfers data between the processor and the interconnect network and between the local memory and the interconnect network over said first data path; and a plurality of I/O controllers, including a first I/O controller, wherein each I/O controller is connected to the second data path of a plurality of the router circuits and wherein each router circuit further includes I/O routing means for transferring data between the I/O controller to which the router circuit is connected and local memory of any of the plurality of processing nodes.
Claim 3
Dependent Claim
95 words
The system according to claim 1 wherein one of the local memories includes a first memory location and wherein the router circuit further includes an external registers circuit, wherein the external registers circuit includes: a plurality of external registers connected to the processor via a data bus; an address translator for calculating, based on an index written to the data bus, an address associated with the first memory location; and transfer means, connected to the plurality of external registers, for transferring data between the first memory location and one of the plurality of external registers.
Claim 4
Dependent Claim
16 words
The system according to claim 2 wherein the router circuit further includes an integrated address centrifuge.
Claim 5
Dependent Claim
27 words
The system according to claim 1 wherein the I/O routing means includes means for forwarding to the I/O controller a message packet received by the router circuit.
Claim 6
Dependent Claim
225 words
A massively parallel processing system, comprising: an interconnect network; a plurality of processing nodes, wherein each processing node includes: a processor; local memory; and a router circuit connected to the interconnect network, the processor and the local memory, wherein the router circuit includes first and second data paths, wherein the router circuit transfers data between the processor and the interconnect network and between the local memory and the interconnect network over said first data path; a peripheral device; and a plurality of I/O controllers, including a first I/O controller, wherein each I/O controller is connected to the second data path of a plurality of the router circuits and wherein each router circuit further includes I/O routing means for transferring data between the I/O controller to which the router circuit is connected and local memory of any of the plurality of processing nodes a plurality of I/O controllers, including a first I/O controller, wherein each I/O controller is connected to a plurality of router circuits, wherein each router circuit further includes means for transferring data between the I/O controller to which the router circuit is connected and local memory of any of the plurality of processing nodes and wherein the first I/O controller includes peripheral interface means for transferring data from the peripheral device to the local memory on one of the plurality of processing nodes.
Claim 7
Dependent Claim
225 words
A massively parallel processing system, comprising: an interconnect network; a plurality of processing nodes, wherein each processing node includes: a processor; local memory; and a router circuit connected to the interconnect network, the processor and the local memory, wherein the router circuit includes first and second data paths, wherein the router circuit transfers data between the processor and the interconnect network and between the local memory and the interconnect network over said first data path; a peripheral device; and a plurality of I/O controllers, including a first I/O controller, wherein each I/O controller is connected to the second data path of a plurality of the router circuits and wherein each router circuit further includes I/O routing means for transferring data between the I/O controller to which the router circuit is connected and local memory of any of the plurality of processing nodes a plurality of I/O controllers, including a first I/O controller, wherein each I/O controller is connected to a plurality of router circuits, wherein each router circuit further includes means for transferring data between the I/O controller to which the router circuit is connected and local memory of any of the plurality of processing nodes and wherein the first I/O controller includes peripheral interface means for transferring data from the peripheral device to the local memory on one of the plurality of processing nodes.
Claim 8
Dependent Claim
29 words
The system according to claim 5, wherein the peripheral interface means includes a serial channel connected to the peripheral device and to one of the plurality of I/O controllers.
Claim 9
Dependent Claim
95 words
The system according to claim 5 wherein one of the local memories includes a first memory location and wherein the router circuit further includes an external registers circuit, wherein the external registers circuit includes: a plurality of external registers connected to the processor via a data bus; an address translator for calculating, based on an index written to the data bus, an address associated with the first memory location; and transfer means, connected to the plurality of external registers, for transferring data between the first memory location and one of the plurality of external registers.
Claim 10
Dependent Claim
16 words
The system according to claim 7 wherein the router circuit further includes an integrated address centrifuge.
Claim 11
Dependent Claim
27 words
The system according to claim 5 wherein the I/O routing means includes means for forwarding to the I/O controller a message packet received by the router circuit.
Claim 12
Independent Claim
177 words
A method of transferring data between a peripheral device and a massively parallel processing system having an interconnect network and a plurality of processing nodes, wherein each processing node includes a processor, local memory and a router circuit connected to the interconnect network, the processor and the local memory, wherein the router circuit includes a first and a second data path, wherein the router circuit transfers data between the processor and the interconnect network and between the local memory and the interconnect network over said first data path: providing an I/O controller; connecting the I/O controller to the second data path of a plurality of router circuits; reading data from the peripheral device; transferring the data read from the peripheral device from the I/O controller to one of the plurality of router circuits connected to the I/O controller; and transferring the data read from the peripheral device from the one of the plurality of router circuits connected to the I/O controller across the interconnect network to the local memory of one of the plurality of processing nodes.
Claim 13
Independent Claim
177 words
A method of transferring data between a peripheral device and a massively parallel processing system having an interconnect network and a plurality of processing nodes, wherein each processing node includes a processor, local memory and a router circuit connected to the interconnect network, the processor and the local memory, wherein the router circuit includes a first and a second data path, wherein the router circuit transfers data between the processor and the interconnect network and between the local memory and the interconnect network over said first data path: providing an I/O controller; connecting the I/O controller to the second data path of a plurality of router circuits; reading data from the peripheral device; transferring the data read from the peripheral device from the I/O controller to one of the plurality of router circuits connected to the I/O controller; and transferring the data read from the peripheral device from the one of the plurality of router circuits connected to the I/O controller across the interconnect network to the local memory of one of the plurality of processing nodes.
Claim 14
Dependent Claim
38 words
The method according to claim 10, wherein the step of reading includes the steps of formatting a packet containing the data read from the peripheral device and sending the packet over a serial channel to the I/O controller.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-25 | 2002-07-27 | 2003-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-25 | 2006-07-27 | 2007-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-25 | 2010-07-27 | 2011-01-26 | $7700.00 | Window Closed / Lapsed |