FIFO memory arrangement including a memory location fill indication

Claim 2

A first-in, first-out memory arrangement comprising: an addressable cyclic memory having N memory locations, wherein an arbitrary number of said N memory locations may be filled at any point in time, where N>1, and mean for determining said arbitrary number and a remaining number of said N memory locations that are unfilled, and responsive to external request signals, for outputting to an output terminal of said first-in, first-out memory arrangement said arbitrary and remaining numbers, in which each of said arbitrary and remaining numbers is a discrete value between 0 and N.

Claim 3

The arrangement set forth in claim 1 further comprising a first address pointer containing an address identifying the next location in said addressable cyclic memory at which a data word is to be stored, and a second address pointer containing an address identifying the next location in said addressable cyclic memory that is to be read, and wherein said means for determining includes means for calculating said arbitrary and remaining numbers as a function of the addresses contained in said first and second address pointers.

Claim 4

The arrangement set forth in claim 2 wherein said means for calculating includes means, operative prior to said arbitrary and remaining numbers being calculated and responsive to the value of the address contained in said first address pointer going from a maximum to minimum address, for prefixing to said first address pointer a predetermined value and, responsive to the address contained in said second address pointer going from a maximum to a minimum address, for removing said predetermined value from said first address pointer and prefixing said predetermined value to said second address pointer.

Claim 5

The arrangement set forth in claim 1 wherein said discrete value is represented by a predetermined number of binary bits comprising a number of low-order bits and a number of high-order bits and wherein said means for determining and outputting includes means, responsive to receipt of other external request signals, for respectively outputting the low-order and high-order bits of said discrete value to said output terminal.

Claim 6

A first-in, first-out memory system operating in conjunction with first and second processors comprising an addressable cyclic memory having a plurality of memory locations, in which an arbitrary number of said memory locations may be filled at any point in time, a first pointer register for supplying an address identifying a memory location at which a data word is to be stored, a second pointer register for supplying an address identifying a memory location which is to be read, means for incrementing said first pointer register by a predetermined value when a word is stored in said addressable cyclic memory and for incrementing said second pointer register by said predetermined value when a word is read from said addressable cyclic memory, means for forming first and second values from the addresses provided by said first and second pointer registers, respectively, for prefixing a predetermined number to said first value whenever the address contained in said first pointer register goes from a maximum to a minimum value and for transferring said prefixed number from said first value to said second value whenever the address in said second pointer register goes from a maximum to a minimum value, means for determining, as a function of said first and second values, said arbitrary number and a corresponding number of said plurality of memory locations which are empty, and means, responsive to receipt of a request signal from said first processor, for outputting to an output terminal said arbitrary number and, responsive to receipt of a request signal from said second processor, for outputting to another output terminal said corresponding number.

Claim 7

A first-in, first-out memory system operating in conjunction with first and second processors comprising an addressable cyclic memory having a plurality of memory locations, in which an arbitrary number of said memory locations may be filled at any point in time, a first pointer register for supplying an address identifying a memory location at which a data word is to be stored, a second pointer register for supplying an address identifying a memory location which is to be read, means for incrementing said first pointer register by a predetermined value when a word is stored in said addressable cyclic memory and for incrementing said second pointer register by said predetermined value when a word is read from said addressable cyclic memory, means for forming first and second values from the addresses provided by said first and second pointer registers, respectively, for prefixing a predetermined number to said first value whenever the address contained in said first pointer register goes from a maximum to a minimum value and for transferring said prefixed number from said first value to said second value whenever the address in said second pointer register goes from a maximum to a minimum value, means for determining, as a function of said first and second values, said arbitrary number and a corresponding number of said plurality of memory locations which are empty, and means, responsive to receipt of a request signal from said first processor, for outputting to an output terminal said arbitrary number and, responsive to receipt of a request signal from said second processor, for outputting to another output terminal said corresponding number.

Claim 8

The arrangement set forth in claim 5 wherein each of said arbitrary and corresponding numbers is represented by a predetermined number of binary bits comprising a number of low-order and high-order bits and wherein said means for outputting includes means for outputting to said output terminal the low-order or high-order bits of said arbitrary number responsive to receipt of a respective first or second request signal from said first processor, and for outputting to said other output terminal the low-order or high-order bits of said corresponding number responsive to receipt of a respective third or fourth request signal from said second processor.

Claim 9

A memory arrangement comprising first and second memories each having a plurality of memory locations, a first processor connected to said first and second memories via a multibit write bus such that a predetermined number of bit leads of said multibit write bus are connected to said first memory and remaining bit leads thereof are connected to said second memory, means contained in each of said first and second memories for determining at least the number of unfilled memory locations in their respective memories, said number being the same for both of said memories and being represented by low-order bits and high-order bits, means contained in said first memory responsive to receipt of a request for outputting to the bit leads connected to said first memory the low-order bits of said number, and means contained in said second memory responsive to receipt of said request for outputting to the remaining bit leads connected to said second memory the high-order bits of said number.

Claim 10

A memory arrangement comprising first and second memories each having a plurality of memory locations, a first processor connected to said first and second memories via a multibit write bus such that a predetermined number of bit leads of said multibit write bus are connected to said first memory and remaining bit leads thereof are connected to said second memory, means contained in each of said first and second memories for determining at least the number of unfilled memory locations in their respective memories, said number being the same for both of said memories and being represented by low-order bits and high-order bits, means contained in said first memory responsive to receipt of a request for outputting to the bit leads connected to said first memory the low-order bits of said number, and means contained in said second memory responsive to receipt of said request for outputting to the remaining bit leads connected to said second memory the high-order bits of said number.

Claim 11

A first-in, first-out memory arrangement comprising, an addressable cyclic memory having N memory locations, in which an arbitrary number of said N memory locations may be filled at any point in time, where N>1, and means for determining said arbitrary number and, responsive to receipt of an external request signal, for outputting to an output terminal of said first-in, first-out memory arrangement said arbitrary number, in which said arbitrary number is a discrete value between 0 and N.

Claim 12

A first-in, first-out memory arrangement comprising, an addressable cyclic memory having N memory locations, in which an arbitrary number of said N memory locations may be filled at any point in time, where N>1, and means for determining said arbitrary number and, responsive to receipt of an external request signal, for outputting to an output terminal of said first-in, first-out memory arrangement said arbitrary number, in which said arbitrary number is a discrete value between 0 and N.

Claim 13

A first-in, first-out memory arrangement comprising, an addressable cyclic memory having N memory locations, in which an arbitrary number of said N memory locations may be unfilled at any point in time, where N>1, and means for determining said arbitrary number and, responsive to receipt of an external request signal, for outputting to an output terminal of said first-in first-out memory arrangement said arbitrary number, in which said arbitrary number is a discrete value between 0 and N.

Claim 14

A first-in, first-out memory arrangement comprising, an addressable cyclic memory having N memory locations, in which an arbitrary number of said N memory locations may be unfilled at any point in time, where N>1, and means for determining said arbitrary number and, responsive to receipt of an external request signal, for outputting to an output terminal of said first-in first-out memory arrangement said arbitrary number, in which said arbitrary number is a discrete value between 0 and N.