EP0460599B1
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Massively parallel processor including queue-based message delivery system
Assignee: TM Patents LP
•
Filing: 1991-06-04
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Granted: 1999-02-10
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Expires: 2011-06-04
Abstract
No abstract record available.
Inventors
- 👤 Steven K. Heller
- 👤 Kevin B. Oliveau
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 04:17
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17356; G06F15/17368; G06F15/17381
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
326 words
A massively parallel computer system comprising: A: a plurality of processing nodes (10), each
processing node including at least one processor
(14(i)), a memory, each processing node receiving
processor control signals for performing processing
operations in connection with data in said memory and
for generating and receiving messages; B: a communications network, (15H, 15L; HC-O-L (11:0),
HC-I-L-(11:0), HC-O-H (11:0), HC-I-H (11:0)) including
a plurality of router nodes interconnected by
communications links, each router node being connected
to a corresponding processing node, the router nodes
being responsive to routing control signals, to receive
messages from said processing nodes and transfer the
messages over the communications links to processing
nodes which are to receive the messages; and C: a controller (5:6) connected to all of said
processing nodes and said router nodes for i. generating processor control signals for
transmission to all of said processing nodes in
parallel to control said processing nodes to: a) establish in parallel a message queue (50) for each
processing node in their respective memories; b) provide messages in parallel for transmission to
said router nodes; c) receive messages in parallel from said router nodes;
and d) append in parallel said received messages to their
respective message queues; said received messages
including an identification of the processing node (10)
and the processor (14(i)) that is the intended
recipient of the message, the message queue in each processing node including a
queue count portion (52) for storing a message count for each processor (14(i)) in the processing node (10),
said controller generating processor control signals
for enabling said processing nodes to increment the
message count in their respective queue count portions
in response to receipt of a message; and ii. generating routing control signals to enable said
router nodes to transfer messages generated by the
processing nodes over said communications links to
their respective destination processing nodes; thereby to enable the processing nodes to, in parallel,
append respective successively-received messages to
respective queues (50).
Claim 2
Dependent Claim
77 words
A system as defined in claim 1 in which each processing
node includes a plurality of processors (14(i)), and in
which each message identifies a processor, said
controller enabling each queue count portion to include
a plurality of count slots (53), each count slot being
associated with a processor, said controller generating
processor control signals enabling the processors to,
in parallel in response to receipt of a message,
increment the message count in their respective count
slot.
Claim 3
Dependent Claim
48 words
A system as defined by claim 1 in which, in the message
queue in each processing node, a queue slot portion
includes a plurality of queue slots, said controller
generating processor control signals enabling received
messages to be stored in successive queue slots in said
queue slot portion.
Claim 4
Dependent Claim
38 words
A system as defined in claim 3 in which
said
controller generates processor control signals
enabling the processors of processing nodes which have
received messages to, in parallel, increment the
message counts in said respective queue count portions.
Claim 5
Dependent Claim
48 words
A system as defined in claim 4 in which the controller
generates router control signals that enable the router
nodes to, in parallel, use the message count in the
queue count portion to identify a slot in the
respective message queue in which a received message is
stored.
Claim 6
Dependent Claim
76 words
A system as defined in claim 5 in which each processing
node further includes a maximum slot count value
identifying a maximum number of queue slots in the
processing node's message queue, the controller
generating processor control signals enabling said
processor nodes to, in parallel in response to receipt
of a message, further use the maximum slot count value
(107) in identifying a slot in the message queue in
which a respective received message is stored.
Claim 7
Dependent Claim
62 words
A system as defined in claim 6 in which the controller
generates processor control signals to enable said
processor nodes (10) to, in parallel in response to
receipt of a message, use the minimum of the respective
message count and the respective maximum slot count
value to identify a slot in the message queue in which
a respective received message is stored.
Claim 8
Dependent Claim
82 words
A system as defined in claim 4 in which each processing
node includes a plurality of processors (14(i)), and in
which each message identifies a processor, each queue
count portion further including a plurality of count
slots, each count slot being associated with a
processor, said controller generating processor control
signals enabling the processor nodes to, in parallel in
response to receipt of respective messages, increment
the messages count in the count slot associated with
the processors identified by the received messages.
Claim 9
Dependent Claim
86 words
A system as defined in claim 8 in which each queue slot
also includes a plurality of processor slots, each
processor slot in each queue slot being associated with
a processor (14(i)) on the respective processing node
(10), said controller generating processor control
signals enabling, in parallel, each message received by
the processor nodes to be stored in the processor slot
associated with the processor identified in the
message, in the queue slot identified by the count
slot associated with the processor identified in the
message.
Claim 10
Dependent Claim
54 words
A system as defined in claim 9 in which each
processor slot is identified by a memory address, said
controller generating processor control signals
enabling, the processing node (10) to, in parallel,
generate addresses to control storage of messages in
each memory in response to their respective message
counts in the queue count portion.
References Cited (Backward Citations)
No citation records indexed.
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