Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
103 words
A work station having a plurality of parallel processors (12a-12n) for sharing jobs of a processing task to be carried out in essentially parallel manner, characterized by register means (21) connected to said processors (12a-12n) and having a plurality of bit positions respectively associated with said processors, each of said processors participating in said processing task being arranged to set the associated bit position of said register means (21) to a predetermined logic state upon completion of its job, and detection means (30a-30n, 32) arranged to generate a completion signal upon the bit positions of said register means achieving a predetermined logic configuration.
Claim 2
Dependent Claim
47 words
A work station according to claim 1, characterized in that said detection means (30a-30n, 32) is arranged to generate said completion signal upon each bit position of said register means (21) associated with a processor participating in said processing task being set to said predetermined logic state.
Claim 3
Dependent Claim
78 words
A work station according to either claim 1 or claim 2, characterized by main processing means (10) and in that said parallel processors serve as slave processors (12a-12n), said completion signal being arranged to be fed to said slave processors for resetting those slave processors which participated in said processing task to a non participating condition, and also being arranged to be fed to said main processing means (10) for indicating thereto that all jobs have been completed.
Claim 4
Dependent Claim
148 words
A work station according to claim 3, characterized in that said register means (21) includes a first register (24) having a plurality of bit positions respectively associated with said plurality of slave processors (12a-12n), and a second register (22) having a plurality of bit positions respectively corresponding to said plurality of slave processors, each slave processor participating in said processing task being arranged to set the associated bit position of said first register (24) to a predetermined logic state upon completion of its job, and said main processing means (10) being arranged to set to a predetermined logic state each bit position of said second register (22) corresponding to a slave processor which is to participate in said processing task, said detection means (30a-30n, 32) being arranged to generate said completion signal upon coincidence of the logic states of all bit positions of said first and second registers.
Claim 5
Dependent Claim
106 words
A work station according to claim 4, including a plurality of gates (30a-30n) respectively corresponding to said plurality of slave processors (12a-12n), each gate being associated with the corresponding bit positions of said first and second registers (24,22) and being arranged to provide an output signal of predetermined logic state in response to both corresponding bit positions being in the same logic state, and a further gate (32) to which are applied the output signals of said plurality of gates (30a-30n), said further gate being arranged to provide said completion signal when all the output signals of said plurality of gates have said predetermined logic state.
Claim 6
Dependent Claim
28 words
A work station according to claim 5, wherein each of said plurality of gates (30a-30n) is an EXCLUSIVE-NOR gate and said further gate (32) is an AND gate.