US5859860A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low overhead input and output boundary scan cells
Assignee: Texas Instruments Inc
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Filing: 1997-07-24
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Granted: 1999-01-12
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Expires: 2017-07-24
Abstract
Abstract Input and output boundary scan cells respectively include latchable input and output buffers (103,40) which respectively utilize the input and output buffers of the integrated circuit in which the boundary scan cells are provided. The latchable input and output buffers provide the input and output boundary scan cells with a low overhead latching function.
Inventors
- 👤 Lee D. Whetsel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:25
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31712; G01R31/31715; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541; G01R31/318572
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
112 words
An electrical circuit, comprising: functional circuitry for performing normal operating functions of the electrical circuit; an input buffer coupled to said functional circuitry for receiving input signals from a source external to said functional circuitry and driving said input signals to a destination within said functional circuitry; a test data path for providing test data; memory circuitry coupled to said test data path for storing test data received from said test data path; and a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including said input buffer and a feedback path connected in parallel with said input buffer.
Claim 2
Dependent Claim
112 words
An electrical circuit, comprising: functional circuitry for performing normal operating functions of the electrical circuit; an input buffer coupled to said functional circuitry for receiving input signals from a source external to said functional circuitry and driving said input signals to a destination within said functional circuitry; a test data path for providing test data; memory circuitry coupled to said test data path for storing test data received from said test data path; and a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including said input buffer and a feedback path connected in parallel with said input buffer.
Claim 3
Dependent Claim
30 words
The circuit of claim 1, wherein said feedback path includes a further buffer cross-coupled with said input buffer, and wherein said further buffer can be overdriven by said input signals.
Claim 4
Dependent Claim
17 words
The circuit of claim 2, including a first switch coupled to an input of said input buffer.
Claim 5
Dependent Claim
18 words
The circuit of claim 3, including a second switch connected between said memory circuitry and said input buffer.
Claim 6
Dependent Claim
33 words
The circuit of claim 4, including a third switch connected in series between said first switch and said input buffer and also connected in series between said second switch and said input buffer.
Claim 7
Dependent Claim
20 words
The circuit of claim 5, wherein one of said switches is one of a transmission gate and a 3-state buffer.
Claim 8
Dependent Claim
16 words
The circuit of claim 1, including a switch coupled to an input of said input buffer.
Claim 9
Dependent Claim
18 words
The circuit of claim 7, wherein said switch is one of a transmission gate and a 3-state buffer.
Claim 10
Dependent Claim
17 words
The circuit of claim 1, including a switch connected between said memory circuitry and said input buffer.
Claim 11
Dependent Claim
18 words
The circuit of claim 9, wherein said switch is one of a transmission gate and a 3-state buffer.
Claim 12
Dependent Claim
78 words
An electrical circuit, comprising: a signal path for carrying a signal used in normal operating functions of the electrical circuit; a test data path; a multiplexer having a first input connected to said signal path and having a second input connected to said test data path and having an output; and circuitry connected to said multiplexer output and cooperable with said multiplexer for permitting test data from said test data path to be latched at said multiplexer output.
Claim 13
Dependent Claim
78 words
An electrical circuit, comprising: a signal path for carrying a signal used in normal operating functions of the electrical circuit; a test data path; a multiplexer having a first input connected to said signal path and having a second input connected to said test data path and having an output; and circuitry connected to said multiplexer output and cooperable with said multiplexer for permitting test data from said test data path to be latched at said multiplexer output.
Claim 14
Dependent Claim
31 words
The circuit of claim 11, wherein said signal path is an output signal path for carrying an output signal of the electrical circuit to a destination external to the electrical circuit.
Claim 15
Dependent Claim
21 words
The circuit of claim 12, wherein said circuitry includes an output buffer for driving said output signal to the external destination.
Claim 16
Dependent Claim
19 words
The circuit of claim 13, wherein said circuitry includes a feedback path connected in parallel with said output buffer.
Claim 17
Dependent Claim
50 words
The circuit of claim 14, wherein said multiplexer includes a switch connected between said second input of said multiplexer and said output of said multiplexer, said switch having a control input for momentarily closing said switch and thereafter opening said switch to latch said test data at said multiplexer output.
Claim 18
Dependent Claim
34 words
The circuit of claim 11, wherein said signal path is an input signal path for carrying an input signal from a source external to the electrical circuit to a destination within the electrical circuit.
Claim 19
Dependent Claim
20 words
The circuit of claim 16, wherein said circuitry includes an input buffer for driving said input signal to the destination.
Claim 20
Dependent Claim
19 words
The circuit of claim 17, wherein said circuitry includes a feedback path connected in parallel with said input buffer.
Claim 21
Dependent Claim
50 words
The circuit of claim 18, wherein said multiplexer includes a switch connected between said second input of said multiplexer and said output of said multiplexer, said switch having a control input for momentarily closing said switch and thereafter opening said switch to latch said test data at said multiplexer output.
Claim 22
Dependent Claim
29 words
The circuit of claim 11, wherein said circuitry includes a buffer having an input connected to said multiplexer output, and a feedback path connected in parallel with said buffer.
Claim 23
Dependent Claim
28 words
The circuit of claim 20, wherein said signal path is a control signal path and said signal selectively enables and disables an output buffer of the electrical circuit.
Claim 24
Dependent Claim
50 words
The circuit of claim 20, wherein said multiplexer includes a switch connected between said second input of said multiplexer and said output of said multiplexer, said switch having a control input for momentarily closing said switch and thereafter opening said switch to latch said test data at said multiplexer output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-11 | 2002-07-13 | 2003-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-11 | 2006-07-13 | 2007-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-11 | 2010-07-13 | 2011-01-12 | $7700.00 | Window Closed / Lapsed |