Semiconductor apparatus including semiconductor integrated circuit and operating method thereof

Claim 2

A semiconductor apparatus comprising a one-chip semiconductor integrated circuit including a logic circuit, a plurality of register means coupled in a cascade to each other and each coupled to said logic circuit, control means coupled to said register means for generating control signals for controlling said register means, system data terminal means coupled to said register means for inputting/outputting system data thereto/therefrom, and test signal terminal means coupled to said control means for receiving and supplying a test signal to said control means, said control means comprising means responsive to said test signal for generating control signals for controlling said register means, said control signals including, a selection signal, a capture clock, a shift clock and a feed clock, each said register means comprising, (a) shift-in means responsive to said shift clock for shifting data from adjacent preceding register means to said register means,

Claim 3

(b) selection means responsive to said selection signal for selecting between (i) data from said system data terminal or said logic circuit means and (ii) said data shifted from said adjacent preceding register means, (c) capture means coupled to said selecting means and responsive to said capture clock for capturing said selected data from said system data terminal or said logic circuit means, (d) shift-out means responsive to said shift clock for shifting said captured data from said register means to adjacent succeeding register means, and (e) data feeding means responsive only to said feed clock for feeding said selected data to said system data terminal means or said logic circuit means.

Claim 4

(b) selection means responsive to said selection signal for selecting between (i) data from said system data terminal or said logic circuit means and (ii) said data shifted from said adjacent preceding register means, (c) capture means coupled to said selecting means and responsive to said capture clock for capturing said selected data from said system data terminal or said logic circuit means, (d) shift-out means responsive to said shift clock for shifting said captured data from said register means to adjacent succeeding register means, and (e) data feeding means responsive only to said feed clock for feeding said selected data to said system data terminal means or said logic circuit means.

Claim 5

The semiconductor apparatus according to claim 1, wherein said control means includes decoding means for decoding the contents of said test signal, and test access port controlling means for varying the control signals to be applied to said plurality of register means depending on the decoded contents.

Claim 6

The semiconductor apparatus according to claim 2, wherein said test access port controlling means comprises means for generating a selection signal, a feed clock signal, a capture clock signal and a non-overlapped shift clock signal of two phases, to apply said selection signal, said feed clock signal and said capture clock signal to said register means and then apply said shift clock signal to said shift register means in a case (i) where the contents of said test signal are a sample test, and to apply only said selection signal and said feed clock signal to all said plurality of register means in a case (ii) where the contents of said test signal are a test of a path through which system data is transmitted.

Claim 7

The semiconductor apparatus according to claim 1, wherein said shift-in means includes state storing means for temporarily storing applied data, and gate means responsive to said shift clock signal for applying the data shifted from the adjacent preceding register means to said state storing means.

Claim 8

The semiconductor apparatus according to claim 4, wherein said capture means includes gate means connected to said selection means and responsive to said capture clock signal for applying the selected data to said state storing means of said shift-in means.

Claim 9

The semiconductor apparatus according to claim 1, wherein said shift-out means includes state storing means for temporarily storing applied data, and gate means connected to said shift-in means and responsive to said shift clock signal for applying the data from said shift-in means to said state storing means.

Claim 10

The semiconductor apparatus according to claim 1, wherein said capture means and said shift-out means include state storing means for temporarily storing applied data, first gate means connected to said selection means and responsive to said capture clock signal for applying the selected data to said state storing means, and second gate means connected to said shift-in means and responsive to said shift clock signal for applying the shifted data to said state storing means.

Claim 11

The semiconductor apparatus according to claim 1, wherein said data feeding means includes state storing means for temporarily storing applied data, and gate means connected to said selection means and responsive to said feed clock signal for applying the selected data to said state storing means.

Claim 12

The semiconductor apparatus according to claim 1, wherein said selection means includes first signal inversion means connected to said system data terminal or said logic circuit, second signal inversion means connected to said shift-in means, third signal inversion means supplied with said selection signal, gate means responsive to an output of said third signal inversion means for passing one of an output of said first signal inversion means and an output of said second signal inversion means, and fourth signal inversion means connected to an output of said gate means.

Claim 13

The semiconductor apparatus according to claim 1, wherein said data feeding means includes means for ANDing said feed clock signal and said selected data.

Claim 14

The semiconductor apparatus according to claim 1, wherein said data feeding means includes signal inversion means supplied with said feed clock signal, and means for ORing an output of said signal inversion means and said selected data.

Claim 15

A test circuit apparatus comprising a connection means in which a system connection is formed for transmitting system data and a test connection is formed for transmitting a test instruction signal which includes a test mode signal for indicating the contents of a test, test data and a test clock signal; and a plurality of semiconductor integrated circuits connected to said connection means, each said semiconductor integrated circuit including: control signal generator means for generating a control signal responsive to the test instruction signal input through said test connection for transmitting the test data; a plurality of system data input/output terminals connected to said system connection; processing means for processing the system data input and output through said system data input/output terminals; and test bus forming means connected between respective system data input/output terminals and the processing means and responsive to said control signal, for forming a test bus operatively connected to said test connection to transmit processed data which has been processed by said processing means or the test data, said control signal generator means including clock signal generator means responsive to the test mode signal included in said test instruction signal for generating a select signal for making selection as to whether the data is applied to said processing means or to a test bus, a capture clock signal for capturing the processed data processed by said processing means, a first shift clock signal for transmitting the test data of the processed data to the test bus, the second shift clock signal and an updated clock signal for applying the test data to said system data output terminal or said processing means; and said test bus forming means including, first latch means responsive to said first shift clock signal for outputting shifted-in data, second latch means connected to an output of said first latch means and responsive to said second shift clock signal for outputting an output of said first latch means to the test bus, selector means connected to the output of said first latch means and either the output of said processing means or the system data input terminal, and responsive to said select signal for selecting the output of said first latch means and either the output of said processing means or the system data input, third latch means connected to an output of said selector means and responsive to said capture clock signal for outputting output data of said selector means to the test bus, and data output means connected to the output of said selector means and responsive to said update clock signal for outputting the output data of said selector means to either the system data output terminal or said processing means.

Claim 16

A test circuit apparatus comprising a connection means in which a system connection is formed for transmitting system data and a test connection is formed for transmitting a test instruction signal which includes a test mode signal for indicating the contents of a test, test data and a test clock signal; and a plurality of semiconductor integrated circuits connected to said connection means, each said semiconductor integrated circuit including: control signal generator means for generating a control signal responsive to the test instruction signal input through said test connection for transmitting the test data; a plurality of system data input/output terminals connected to said system connection; processing means for processing the system data input and output through said system data input/output terminals; and test bus forming means connected between respective system data input/output terminals and the processing means and responsive to said control signal, for forming a test bus operatively connected to said test connection to transmit processed data which has been processed by said processing means or the test data, said control signal generator means including clock signal generator means responsive to the test mode signal included in said test instruction signal for generating a select signal for making selection as to whether the data is applied to said processing means or to a test bus, a capture clock signal for capturing the processed data processed by said processing means, a first shift clock signal for transmitting the test data of the processed data to the test bus, the second shift clock signal and an updated clock signal for applying the test data to said system data output terminal or said processing means; and said test bus forming means including, first latch means responsive to said first shift clock signal for outputting shifted-in data, second latch means connected to an output of said first latch means and responsive to said second shift clock signal for outputting an output of said first latch means to the test bus, selector means connected to the output of said first latch means and either the output of said processing means or the system data input terminal, and responsive to said select signal for selecting the output of said first latch means and either the output of said processing means or the system data input, third latch means connected to an output of said selector means and responsive to said capture clock signal for outputting output data of said selector means to the test bus, and data output means connected to the output of said selector means and responsive to said update clock signal for outputting the output data of said selector means to either the system data output terminal or said processing means.