Stable output bias current circuitry and method for low-impedance CMOS output stage

Claim 2

A CMOS output circuit including a bias circuit, the bias circuit including a first resistor coupled between a first supply voltage conductor and a first conductor, a first first-conductivity-type MOSFET having a source coupled to the first supply voltage conductor, a gate coupled to the first conductor, and a drain coupled to a second conductor, a second first-conductivity-type MOSFET having a source coupled to the first conductor, a gate coupled to the second conductor, and a drain coupled to a drain and gate of a first second-conductivity-type o current mirror control MOSFET having a source coupled to a second supply voltage conductor, and a first second-conductivity-type current mirror output MOSFET having a gate coupled to the gate of the first second-conductivity-type current mirror control MOSFET, a source coupled to the second supply voltage conductor, and a drain coupled to the second conductor, wherein the first first-conductivity-type MOSFET is biased at the edge of its strong inversion condition, the improvement comprising: (a) an error amplifier including i. a first second-conductivity-type input MOSFET, a gate of the first second-conductivity-type input MOSFET being coupled to a first input terminal, ii. a second second-conductivity-type input MOSFET, a gate of the second second-conductivity-type input MOSFET being coupled to a second input terminal, iii. a second second-conductivity-type current mirror output MOSFET having a gate coupled to the gate of the first second-conductivity-type current mirror control MOSFET, a source coupled to the second supply voltage conductor, and a drain coupled to sources of the first and second second-conductivity-type input MOSFETs, iv. a first resistive load coupled between the first supply voltage conductor and a drain of the first second-conductivity-type input MOSFET; v. a second resistive load coupled between the first supply voltage conductor and a drain of the second second-conductivity-type input MOSFET; and (b) a first-conductivity-type output MOSFET having a gate coupled to the drain of the second second-conductivity-type input MOSFET, a source coupled to the first supply voltage conductor, and a drain coupled to an output terminal, a voltage produced by the error amplifier on the gate of the first-conductivity-type output MOSFET producing a stable quiescent bias current in the first-conductivity-type output MOSFET which is a predetermined multiple of a bias current flowing through the first first-conductivity-type MOSFET to cause the first-conductivity-type output MOSFET to be biased at the edge of its strong inversion condition similarly to the first first-conductivity-type MOSFET, wherein a ratio of a resistance of the first resistive load to a resistance of the second resistive load is equal to (1-e)/(1+e) and a ratio of the channel width of the first second-conductivity-type input MOSFET to a channel width of the second second-conductivity-type MOSFET is equal to (1+e)/(1-e) wherein e has a value greater than 0 and less than 1 to increase the amount of gate-to-source voltage swing available to drive the first-conductivity-type output MOSFET proportionately to e.

Claim 3

The CMOS output circuit of claim 1 wherein the first conductivity type is P type and the second conductivity type is N type and the output MOSFET is a pull-up MOSFET.

Claim 4

The CMOS output circuit of claim 1 wherein the first conductivity type is N type and the second conductivity type is P type and the output MOSFET is a pull-down MOSFET.

Claim 5

A CMOS output circuit including a bias circuit, the bias circuit including a first resistor coupled between a first supply voltage conductor and a first conductor, a first first-conductivity-type MOSFET having a source coupled to the first supply voltage conductor, a gate coupled to the first conductor, and a drain coupled to a second conductor, a second first-conductivity-type MOSFET having a source coupled to the first conductor, a gate coupled to the second conductor, and a drain coupled to a drain and gate of a first second-conductivity-type current mirror control MOSFET having a source coupled to a second supply voltage conductor, and a first second-conductivity-type current mirror output MOSFET having a gate coupled to the gate of the first second-conductivity-type current mirror control MOSFET, a source coupled to the second supply voltage conductor, and a drain coupled to the second conductor, the improvement comprising: (a) an error amplifier including i. first and second second-conductivity-type input MOSFETs, a gate of the first second-conductivity-type input MOSFET being coupled to a first input terminal, a gate of the second second-conductivity-type input MOSFET being coupled to a second input terminal, ii. a second second-conductivity-type current mirror output transistor having a gate coupled to the gate of the first second-conductivity-type current mirror control MOSFET, a source coupled to the second supply voltage conductor, and a drain coupled to sources of the first and second second-conductivity-type input MOSFETs, and iii. a first resistive load coupled between the first supply voltage conductor and a drain of the first second-conductivity-type input MOSFET, iv. a second resistive load coupled between a drain of the second second-conductivity-type input MOSFET and a third conductor, v. a third resistive load coupled between the third conductor and the first supply voltage conductor; (b) a first first-conductivity-type output MOSFET having a gate coupled to the drain of the second second-conductivity-type input MOSFET, a source coupled to the first supply voltage conductor, and a drain coupled to an output terminal; and (c) a second first-conductivity-type output MOSFET having a source coupled to the first supply voltage conductor, a gate coupled to the third conductor, and a drain coupled to the output conductor, a voltage produced by the error amplifier on the gate of the second first-conductivity-type output MOSFET producing a stable quiescent bias current in the second first-conductivity-type output MOSFET which is a predetermined multiple of a bias current flowing through the first first-conductivity-type MOSFET to cause the second first-conductivity-type output MOSFET to be biased at the edge of its strong inversion condition similarly to the first first-conductivity-type MOSFET.

Claim 6

A CMOS output circuit including a bias circuit, the bias circuit including a first resistor coupled between a first supply voltage conductor and a first conductor, a first first-conductivity-type MOSFET having a source coupled to the first supply voltage conductor, a gate coupled to the first conductor, and a drain coupled to a second conductor, a second first-conductivity-type MOSFET having a source coupled to the first conductor, a gate coupled to the second conductor, and a drain coupled to a drain and gate of a first second-conductivity-type current mirror control MOSFET having a source coupled to a second supply voltage conductor, and a first second-conductivity-type current mirror output MOSFET having a gate coupled to the gate of the first second-conductivity-type current mirror control MOSFET, a source coupled to the second supply voltage conductor, and a drain coupled to the second conductor, the improvement comprising: (a) an error amplifier including i. first and second second-conductivity-type input MOSFETs, a gate of the first second-conductivity-type input MOSFET being coupled to a first input terminal, a gate of the second second-conductivity-type input MOSFET being coupled to a second input terminal, ii. a second second-conductivity-type current mirror output transistor having a gate coupled to the gate of the first second-conductivity-type current mirror control MOSFET, a source coupled to the second supply voltage conductor, and a drain coupled to sources of the first and second second-conductivity-type input MOSFETs, and iii. a first resistive load coupled between the first supply voltage conductor and a drain of the first second-conductivity-type input MOSFET, iv. a second resistive load coupled between a drain of the second second-conductivity-type input MOSFET and a third conductor, v. a third resistive load coupled between the third conductor and the first supply voltage conductor; (b) a first first-conductivity-type output MOSFET having a gate coupled to the drain of the second second-conductivity-type input MOSFET, a source coupled to the first supply voltage conductor, and a drain coupled to an output terminal; and (c) a second first-conductivity-type output MOSFET having a source coupled to the first supply voltage conductor, a gate coupled to the third conductor, and a drain coupled to the output conductor, a voltage produced by the error amplifier on the gate of the second first-conductivity-type output MOSFET producing a stable quiescent bias current in the second first-conductivity-type output MOSFET which is a predetermined multiple of a bias current flowing through the first first-conductivity-type MOSFET to cause the second first-conductivity-type output MOSFET to be biased at the edge of its strong inversion condition similarly to the first first-conductivity-type MOSFET.

Claim 7

The CMOS output circuit of claim 4 wherein the channel-width-to-channel-length ratio of the first first-conductivity-type output MOSFET is substantially less than the channel-width-to-channel-length ratio of the second first-conductivity-type output MOSFET to prevent a quiescent bias current in the first first-conductivity-type output MOSFET from being excessively large in the event of a large input offset voltage in the error amplifier.

Claim 8

The CMOS output of claim 5 wherein the first resistive load has a resistance proportional to the resistance of the first resistor divided by a first scale factor k, the second resistive load has a resistance proportional to a second scale factor c multiplied by the resistance of the first resistor divided by the first scale factor k, and the third resistive load has a resistance proportional to the resistance of the first resistor multiplied by (1-c)/k to bias the second first-conductivity-type output MOSFET at the edge of its strong inversion condition o similarly to the first first-conductivity-type MOSFET.

Claim 9

A CMOS output circuit including a bias circuit, the bias circuit including a first resistor coupled between a first supply voltage conductor and a first conductor, a first first-conductivity-type MOSFET having a source coupled to the first supply voltage conductor, a gate coupled to the first conductor, and a drain coupled to a second conductor, a second first-conductivity-type MOSFET having a source coupled to the first conductor, a gate coupled to the second conductor, and a drain coupled to a drain and gate of a first second-conductivity-type current mirror control MOSFET having a source coupled to a second supply voltage conductor, and a first second-conductivity-type current mirror output MOSFET having a gate coupled to the gate of the first second-conductivity-type current mirror control MOSFET, a source coupled to the second supply voltage conductor, and a drain coupled to the second conductor, the improvement comprising: (a) an error amplifier including i. first and second second-conductivity-type input MOSFETs, a gate of the first second-conductivity-type input MOSFET being coupled to a first input terminal, a gate of the second second-conductivity-type input MOSFET being coupled to a second input terminal, ii. a second second-conductivity-type current mirror output transistor having a gate coupled to the gate of the first second-conductivity-type current mirror control MOSFET, a source coupled to the second supply voltage conductor, and a drain coupled to sources of the first and second second-conductivity-type input MOSFETS, and iii. a first resistive load coupled between the first supply voltage conductor and a drain of the first second-conductivity-type input MOSFET, iv. a second resistive load coupled between a drain of the second second-conductivity-type input MOSFET and a third conductor, v. a third resistive load coupled between the third conductor and the first supply voltage conductor; (b) a first first-conductivity-type output MOSFET having a gate coupled to the drain of the second second-conductivity-type input MOSFET, a source coupled to the first supply voltage conductor, and a drain coupled to an output terminal; and (c) a second first-conductivity-type output MOSFET having a source coupled to the first supply voltage conductor, a gate coupled to the third conductor, and a drain coupled to the output conductor, a voltage produced by the error amplifier on the gate of the second first-conductivity-type output MOSFET producing a stable quiescent bias current in the second first-conductivity-type output MOSFET which is a predetermined multiple of a bias current flowing through the first first-conductivity-type MOSFET to cause the second first-conductivity-type output MOSFET to be biased at the edge of its strong inversion condition similarly to the first first-conductivity-type MOSFET, wherein a ratio of a resistance of the first resistive load to a resistance of the second resistive load is equal to (1-e)/(1+e), a ratio of the first resistive load to a resistance of the third resistive load is also equal to (1-e)/(1+e), and a ratio of the channel width of the first second-conductivity-type input MOSFET to a channel width of the second second-conductivity-type MOSFET is equal to (1+e)/(1-e), wherein e has a value greater than 0 and less than 1 to increase the amount of gate-to-source voltage swing available to drive the first-conductivity-type output MOSFET proportionately to e.

Claim 10

A CMOS output circuit including a bias circuit, the bias circuit including a first resistor coupled between a first supply voltage conductor and a first conductor, a first first-conductivity-type MOSFET having a source coupled to the first supply voltage conductor, a gate coupled to the first conductor, and a drain coupled to a second conductor, a second first-conductivity-type MOSFET having a source coupled to the first conductor, a gate coupled to the second conductor, and a drain coupled to a drain and gate of a first second-conductivity-type current mirror control MOSFET having a source coupled to a second supply voltage conductor, and a first second-conductivity-type current mirror output MOSFET having a gate coupled to the gate of the first second-conductivity-type current mirror control MOSFET, a source coupled to the second supply voltage conductor, and a drain coupled to the second conductor, the improvement comprising: (a) an error amplifier including i. first and second second-conductivity-type input MOSFETs, a gate of the first second-conductivity-type input MOSFET being coupled to a first input terminal, a gate of the second second-conductivity-type input MOSFET being coupled to a second input terminal, ii. a second second-conductivity-type current mirror output transistor having a gate coupled to the gate of the first second-conductivity-type current mirror control MOSFET, a source coupled to the second supply voltage conductor, and a drain coupled to sources of the first and second second-conductivity-type input MOSFETS, and iii. a first resistive load coupled between the first supply voltage conductor and a drain of the first second-conductivity-type input MOSFET, iv. a second resistive load coupled between a drain of the second second-conductivity-type input MOSFET and a third conductor, v. a third resistive load coupled between the third conductor and the first supply voltage conductor; (b) a first first-conductivity-type output MOSFET having a gate coupled to the drain of the second second-conductivity-type input MOSFET, a source coupled to the first supply voltage conductor, and a drain coupled to an output terminal; and (c) a second first-conductivity-type output MOSFET having a source coupled to the first supply voltage conductor, a gate coupled to the third conductor, and a drain coupled to the output conductor, a voltage produced by the error amplifier on the gate of the second first-conductivity-type output MOSFET producing a stable quiescent bias current in the second first-conductivity-type output MOSFET which is a predetermined multiple of a bias current flowing through the first first-conductivity-type MOSFET to cause the second first-conductivity-type output MOSFET to be biased at the edge of its strong inversion condition similarly to the first first-conductivity-type MOSFET, wherein a ratio of a resistance of the first resistive load to a resistance of the second resistive load is equal to (1-e)/(1+e), a ratio of the first resistive load to a resistance of the third resistive load is also equal to (1-e)/(1+e), and a ratio of the channel width of the first second-conductivity-type input MOSFET to a channel width of the second second-conductivity-type MOSFET is equal to (1+e)/(1-e), wherein e has a value greater than 0 and less than 1 to increase the amount of gate-to-source voltage swing available to drive the first-conductivity-type output MOSFET proportionately to e.

Claim 11

The CMOS output circuit of claim 7 wherein the channel-width-to-channel-length ratio of the first first-conductivity-type output MOSFET is substantially less than the channel-width-to-channel-length ratio of the second first-conductivity-type output MOSFET to prevent a quiescent bias current in the first first-conductivity-type output MOSFET from being excessively large in the event of a large input offset voltage in the error amplifier.