US5220288A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Continuous-time differential amplifier with low offset voltage
Assignee: Motorola Solutions Inc
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Filing: 1992-06-01
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Granted: 1993-06-15
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Expires: 2012-06-01
Abstract
Abstract A continuous-time differential amplifier (52, 100) preserves fast settling time while reducing a relatively-high offset voltage-normally associated with a continuous-time differential amplifier using MOS load transistors. The differential amplifier (52, 100) includes a first transistor (81) biased as a current source to provide current into emitters of second (82) and third (83) emitter-coupled input transistors. Fourth (84) and fifth (85) load transistors are respectively coupled between collectors of the second (82) and third (83) input transistors and a power supply voltage terminal. An amplifier (70) having a positive input terminal coupled to the collector of the second input transistor (82) and a negative input terminal receiving a bias voltage biases the control electrodes of the load transistors (84, 85). The amplifier (70) increases the effective transconductance of the load transistors (84, 85) to allow larger control electrode areas, which reduces the effect of transistor mismatch.
Inventors
- 👤 Todd L. Brooks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:03
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45479; H03F3/45632; H03F3/45636; H03F3/45641; H03F3/45659; H03F2203/00; H03F2203/45; H03F2203/45508; H03F2203/45658
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
410 words
A continuous-time differential amplifier with low offset voltage comprising: a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving a first bias voltage, and a second current electrode; a second transistor having an emitter coupled to said second current electrode of said first transistor, a base for receiving a negative input signal, and a collector; a third transistor having an emitter coupled to said second current electrode of said first transistor, a base for receiving a positive input voltage, and a collector for providing an output signal; a fourth transistor having a first current electrode coupled to said collector of said second transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal; a fifth transistor having a first current electrode coupled to said collector of said third transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal; an amplifier having a positive input terminal coupled to said collector of said second transistor, a negative input terminal for receiving a second bias voltage, and an output terminal coupled to said control electrodes of said fourth and fifth transistors; and bias means for providing said second bias voltage, said bias means comprising: a sixth transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode, and a second current electrode; a seventh transistor having a first current electrode coupled to said second current electrode of said sixth transistor, a control electrode coupled to said second current electrode of said sixth transistor, and a second current electrode coupled for providing said second bias voltage; an eighth transistor having a first current electrode coupled to said second current electrode of said seventh transistor, a control electrode coupled to said second current electrode of said seventh transistor, and a second current electrode coupled to said second power supply voltage terminal; a ninth transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode for receiving said first bias voltage, and a second current electrode coupled to said control electrode of said sixth transistor; and a tenth transistor having a first current electrode coupled to said second current electrode of said ninth transistor, a control electrode coupled to said second current electrode of said seventh transistor, and a second current electrode coupled to said second power supply voltage terminal.
Claim 2
Dependent Claim
410 words
A continuous-time differential amplifier with low offset voltage comprising: a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving a first bias voltage, and a second current electrode; a second transistor having an emitter coupled to said second current electrode of said first transistor, a base for receiving a negative input signal, and a collector; a third transistor having an emitter coupled to said second current electrode of said first transistor, a base for receiving a positive input voltage, and a collector for providing an output signal; a fourth transistor having a first current electrode coupled to said collector of said second transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal; a fifth transistor having a first current electrode coupled to said collector of said third transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal; an amplifier having a positive input terminal coupled to said collector of said second transistor, a negative input terminal for receiving a second bias voltage, and an output terminal coupled to said control electrodes of said fourth and fifth transistors; and bias means for providing said second bias voltage, said bias means comprising: a sixth transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode, and a second current electrode; a seventh transistor having a first current electrode coupled to said second current electrode of said sixth transistor, a control electrode coupled to said second current electrode of said sixth transistor, and a second current electrode coupled for providing said second bias voltage; an eighth transistor having a first current electrode coupled to said second current electrode of said seventh transistor, a control electrode coupled to said second current electrode of said seventh transistor, and a second current electrode coupled to said second power supply voltage terminal; a ninth transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode for receiving said first bias voltage, and a second current electrode coupled to said control electrode of said sixth transistor; and a tenth transistor having a first current electrode coupled to said second current electrode of said ninth transistor, a control electrode coupled to said second current electrode of said seventh transistor, and a second current electrode coupled to said second power supply voltage terminal.
Claim 3
Dependent Claim
301 words
A continuous-time differential amplifier with low offset voltage comprising: a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving a first bias voltage, and a second current electrode; a second transistor having an emitter coupled to said second current electrode of said first transistor, a base for receiving a negative input signal, and a collector; a third transistor having an emitter coupled to said second current electrode of said first transistor, a base for receiving a positive input voltage, and a collector for providing an output signal; a fourth transistor having a first current electrode coupled to said collector of said second transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal; a fifth transistor having a first current electrode coupled to said collector of said third transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal; and an amplifier having a positive input terminal coupled to said collector of said second transistor, a negative input terminal for receiving a second bias voltage, and an output terminal coupled to said control electrodes of said fourth and fifth transistors, said amplifier comprising: an amplifier stage for selectively diverting a first current in response to differences in voltage between said positive input terminal of said amplifier and said negative input terminal of said amplifier, and for providing a voltage at said output terminal of said amplifier in response thereto; means for providing a reference current proportional to a second current conducted by a sixth transistor biased by said first bias voltage minus a substrate collector current of a seventh lateral bipolar transistor; and means for mirroring said reference current to said amplifier stage to provide said first current.
Claim 4
Dependent Claim
301 words
A continuous-time differential amplifier with low offset voltage comprising: a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving a first bias voltage, and a second current electrode; a second transistor having an emitter coupled to said second current electrode of said first transistor, a base for receiving a negative input signal, and a collector; a third transistor having an emitter coupled to said second current electrode of said first transistor, a base for receiving a positive input voltage, and a collector for providing an output signal; a fourth transistor having a first current electrode coupled to said collector of said second transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal; a fifth transistor having a first current electrode coupled to said collector of said third transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal; and an amplifier having a positive input terminal coupled to said collector of said second transistor, a negative input terminal for receiving a second bias voltage, and an output terminal coupled to said control electrodes of said fourth and fifth transistors, said amplifier comprising: an amplifier stage for selectively diverting a first current in response to differences in voltage between said positive input terminal of said amplifier and said negative input terminal of said amplifier, and for providing a voltage at said output terminal of said amplifier in response thereto; means for providing a reference current proportional to a second current conducted by a sixth transistor biased by said first bias voltage minus a substrate collector current of a seventh lateral bipolar transistor; and means for mirroring said reference current to said amplifier stage to provide said first current.
Claim 5
Dependent Claim
312 words
The differential amplifier of claim 2 wherein said providing means comprises: said sixth transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode for receiving said first bias voltage, and a second current electrode; said seventh lateral bipolar transistor having an emitter coupled to said second current electrode of said sixth transistor, a base, and a collector for providing a first voltage to said mirroring means; an eighth transistor having a first current electrode coupled to said collector of said seventh lateral bipolar transistor, a control electrode coupled to said collector of said seventh lateral bipolar transistor, and a second current electrode for providing a second voltage to said mirroring means; a ninth transistor having a first current electrode coupled to said second current electrode of said eighth transistor, a control electrode coupled to said second current electrode of said eighth transistor, and a second current electrode coupled to said second power supply voltage terminal; a tenth transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode for receiving said first bias voltage, and a second current electrode; an eleventh lateral bipolar transistor having an emitter coupled to said second current electrode of said tenth transistor, a base, and a collector coupled to said base of said seventh bipolar transistor and to said base of said eleventh lateral bipolar transistor; a twelfth transistor having a first current electrode coupled to said collector of said eleventh lateral bipolar transistor, a control electrode coupled to said first current electrode thereof, and a second current electrode; and a thirteenth transistor having a first current electrode coupled to said second current electrode of said twelfth transistor, a control electrode coupled to said second current electrode of said twelfth transistor, and a second current electrode coupled to said second power supply voltage terminal.
Claim 6
Dependent Claim
19 words
The differential amplifier of claim 2 wherein said second and third transistors are characterized as being lateral bipolar transistors.
Claim 7
Dependent Claim
323 words
A signal processing system comprising: a bandgap voltage reference circuit providing a bandgap reference voltage at an output thereof; a differential amplifier having a positive terminal for receiving said bandgap reference voltage, a negative input terminal, and an output terminal for providing a reference voltage; means coupled to said differential amplifier for setting a gain thereof; and data conversion means coupled to said differential amplifier for performing at least one data conversion operation referenced to said reference voltage; said differential amplifier further comprising: an amplifier having a positive input terminal, a negative input terminal for receiving a bias voltage thereon, and an output terminal; first and second emitter-coupled bipolar transistors each having a collector and respectively receiving a first and second input signals at bases thereof; a third transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving a second bias voltage, and a second current electrode coupled to said emitters of said first and second lateral bipolar transistors; and fourth and fifth load transistors respectively coupled between said collectors of said first and second bipolar transistors and a second power supply voltage terminal and having control electrodes coupled to said output terminal of said amplifier; said collectors of said first and second bipolar transistors providing first and second output terminals of said differential amplifier, wherein said amplifier comprises: an amplifier stage for selectively diverting a first current in response to differences in voltage between said positive input terminal of said amplifier and said negative input terminal of said amplifier, and for providing a voltage at said output terminal of said amplifier in response thereto; means for providing a reference current proportional to a second current conducted by a sixth transistor biased by said second bias voltage minus a substrate collector current of a seventh lateral bipolar transistor; and means for mirroring said reference current to said amplifier stage to provide said first current.
Claim 8
Dependent Claim
323 words
A signal processing system comprising: a bandgap voltage reference circuit providing a bandgap reference voltage at an output thereof; a differential amplifier having a positive terminal for receiving said bandgap reference voltage, a negative input terminal, and an output terminal for providing a reference voltage; means coupled to said differential amplifier for setting a gain thereof; and data conversion means coupled to said differential amplifier for performing at least one data conversion operation referenced to said reference voltage; said differential amplifier further comprising: an amplifier having a positive input terminal, a negative input terminal for receiving a bias voltage thereon, and an output terminal; first and second emitter-coupled bipolar transistors each having a collector and respectively receiving a first and second input signals at bases thereof; a third transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving a second bias voltage, and a second current electrode coupled to said emitters of said first and second lateral bipolar transistors; and fourth and fifth load transistors respectively coupled between said collectors of said first and second bipolar transistors and a second power supply voltage terminal and having control electrodes coupled to said output terminal of said amplifier; said collectors of said first and second bipolar transistors providing first and second output terminals of said differential amplifier, wherein said amplifier comprises: an amplifier stage for selectively diverting a first current in response to differences in voltage between said positive input terminal of said amplifier and said negative input terminal of said amplifier, and for providing a voltage at said output terminal of said amplifier in response thereto; means for providing a reference current proportional to a second current conducted by a sixth transistor biased by said second bias voltage minus a substrate collector current of a seventh lateral bipolar transistor; and means for mirroring said reference current to said amplifier stage to provide said first current.
Claim 9
Dependent Claim
312 words
The differential amplifier of claim 5 wherein said providing means comprises: said sixth transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode for receiving said second bias voltage, and a second current electrode; said seventh lateral bipolar transistor having an emitter coupled to said second current electrode of said sixth transistor, a base, and a collector for providing a first voltage to said mirroring means; an eighth transistor having a first current electrode coupled to said collector of said seventh lateral bipolar transistor, a control electrode coupled to said collector of said seventh lateral bipolar transistor, and a second current electrode for providing a second voltage to said mirroring means; a ninth transistor having a first current electrode coupled to said second current electrode of said eighth transistor, a control electrode coupled to said second current electrode of said eighth transistor, and a second current electrode coupled to said second power supply voltage terminal; a tenth transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode for receiving said second bias voltage, and a second current electrode; an eleventh lateral bipolar transistor having an emitter coupled to said second current electrode of said tenth transistor, a base, and a collector coupled to said base of said seventh bipolar transistor and to said base of said eleventh lateral bipolar transistor; a twelfth transistor having a first current electrode coupled to said collector of said eleventh lateral bipolar transistor, a control electrode coupled to said first current electrode thereof, and a second current electrode; and a thirteenth transistor having a first current electrode coupled to said second current electrode of said twelfth transistor, a control electrode coupled to said second current electrode of said twelfth transistor, and a second current electrode coupled to said second power supply voltage terminal.
Claim 10
Dependent Claim
21 words
The differential amplifier of claim 5 wherein said first and second emitter-coupled bipolar transistors are characterized as being lateral bipolar transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-14 | 1996-12-14 | 1997-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-14 | 2000-12-14 | 2001-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-14 | 2004-12-14 | 2005-06-15 | $7700.00 | Window Closed / Lapsed |