US4333058A — Operational amplifier employing complementary fie…

Claim 1

Independent Claim 499 words

An amplifying circuit comprising: first and second supply terminals for receiving relatively positive and relatively negative operating potentials, respectively; inverting and non-inverting input terminals for receiving input signals thereat, and a signal output terminal; a first differential-input amplifier means including: first and second field-effect transistors, of P-channel conductivity type and in long-tailed pair connection, having respective gate electrodes to which said inverting and non-inverting input terminals respectively connect, having respective source electrodes connected to a tail connection, and having respective drain electrodes, means for supplying a first tail current connected between the tail connection of said first differential-input amplifier means and said first supply terminal, first current mirror amplifying means having an input and an output connection, and having a common connection to which said second supply terminal connects, means for connecting the input connection of said first current mirror amplifying means to the drain electrode of said first transistor, and an output connection of said first differential-input amplifier means at which output resistance is exhibited responsive to the connections of the output connection of said first current mirror amplifying means and the drain electrode of said second transistor thereto; a second differential-input amplifier including: third and fourth field-effect transistors, of N-channel conductivity type and in long-tailed pair connection, having respective gate electrodes to which said inverting and non-inverting input terminals respectively connect, having respective source electrodes connected to a tail connection, and having respective drain electrodes, means for supplying a second tail current connected between the tail connection of said second differential-input amplifier means and said second supply terminal; second current mirror amplifying means having an input and an output connection, and having a common connection to which said first supply terminal connects, means for connecting the input connection of said second current mirror amplifying means to the drain-electrode of said third transistor, and an output connection of said second differential-input amplifier means at which output resistance is exhibited responsive to the connections of the output connection of said second current mirror amplifying means and the drain electrode of said fourth transistor thereto; output amplifier means including first and second input connections for providing respective relatively high resistances as compared to the output resistances of the output connections of said first and second differential-input amplifier means, respectively, and fifth and sixth field-effect transistors of N-channel and P-channel type, respectively, each in common-source amplifier configuration having respective source electrodes directly connected to said second and first supply terminals respectively having respective drain electrodes connected to said signal output terminal, and having respective gate electrodes serving as the first and second input connections, respectively, of said output amplifier means; means for directly connecting the output connection of said first differential-input amplifier means to the first input connection of said output amplifier means without substantially reducing the resistance exhibited thereat; and means for directly connecting the output connection of said second differential-input amplifier means to the second input connection of said output amplifier means without substantially reducing the resistance exhibited thereat.

Claim 2

Dependent Claim 499 words

An amplifying circuit comprising: first and second supply terminals for receiving relatively positive and relatively negative operating potentials, respectively; inverting and non-inverting input terminals for receiving input signals thereat, and a signal output terminal; a first differential-input amplifier means including: first and second field-effect transistors, of P-channel conductivity type and in long-tailed pair connection, having respective gate electrodes to which said inverting and non-inverting input terminals respectively connect, having respective source electrodes connected to a tail connection, and having respective drain electrodes, means for supplying a first tail current connected between the tail connection of said first differential-input amplifier means and said first supply terminal, first current mirror amplifying means having an input and an output connection, and having a common connection to which said second supply terminal connects, means for connecting the input connection of said first current mirror amplifying means to the drain electrode of said first transistor, and an output connection of said first differential-input amplifier means at which output resistance is exhibited responsive to the connections of the output connection of said first current mirror amplifying means and the drain electrode of said second transistor thereto; a second differential-input amplifier including: third and fourth field-effect transistors, of N-channel conductivity type and in long-tailed pair connection, having respective gate electrodes to which said inverting and non-inverting input terminals respectively connect, having respective source electrodes connected to a tail connection, and having respective drain electrodes, means for supplying a second tail current connected between the tail connection of said second differential-input amplifier means and said second supply terminal; second current mirror amplifying means having an input and an output connection, and having a common connection to which said first supply terminal connects, means for connecting the input connection of said second current mirror amplifying means to the drain-electrode of said third transistor, and an output connection of said second differential-input amplifier means at which output resistance is exhibited responsive to the connections of the output connection of said second current mirror amplifying means and the drain electrode of said fourth transistor thereto; output amplifier means including first and second input connections for providing respective relatively high resistances as compared to the output resistances of the output connections of said first and second differential-input amplifier means, respectively, and fifth and sixth field-effect transistors of N-channel and P-channel type, respectively, each in common-source amplifier configuration having respective source electrodes directly connected to said second and first supply terminals respectively having respective drain electrodes connected to said signal output terminal, and having respective gate electrodes serving as the first and second input connections, respectively, of said output amplifier means; means for directly connecting the output connection of said first differential-input amplifier means to the first input connection of said output amplifier means without substantially reducing the resistance exhibited thereat; and means for directly connecting the output connection of said second differential-input amplifier means to the second input connection of said output amplifier means without substantially reducing the resistance exhibited thereat.

Claim 3

Dependent Claim 213 words

The amplifying circuit of claim 1 wherein said first current mirror amplifying means comprises: seventh and eighth field-effect transistors of N-channel conductivity type, each having source, drain and gate electrodes; the respective source electrodes of said seventh and eighth transistors connecting to the common terminal of said first current mirror amplifying means, the drain electrode of said seventh transistor serving as the input connection thereof, and the drain electrode of said eighth transistor serving as the output connection thereof; and means connected between the drain electrode of said seventh transistor and the respective gate electrodes of said seventh and eighth transistors for maintaining the potential therebetween in predetermined relationship; and wherein said second current mirror amplifying means comprises: ninth and tenth field-effect transistors of P-channel conductivity type, each having source, drain, and gate electrodes, the respective source electrodes of said ninth and tenth transistors connecting to the common terminal of said second current mirror amplifying means, the drain electrode of said ninth transistor serving as the input connection thereof, and the drain electrode of said tenth transistor serving as the output connection thereof; and means connected between the drain electrode of said ninth transistor and the respective gate electrodes of said ninth and tenth transistors for maintaining the potential therebetween in predetermined relationship.

Claim 4

Dependent Claim 103 words

The amplifying circuit of claim 1 or 2 wherein said means for supplying a first tail current includes a further P-channel field-effect transistor having a drain electrode connected for supplying said first tail current, having a source electrode connected to said first supply terminal, and having a gate electrode connected to said second supply terminal; and wherein said means for supplying a second tail current includes a further N-channel field-effect transistor, having a drain electrode connected for supplying said second tail current, having a source electrode connected to said second supply terminal, and having a gate electrode connected to said first supply terminal.

Claim 5

Dependent Claim 60 words

The amplifying circuit of claim 1 or 2 further comprising: means included in said means for supplying a first tail current for varying the first tail current responsive to a first control signal applied thereto; means included in said means for supplying a second tail current for varying the second tail current responsive to a second control signal applied thereto.

Claim 6

Dependent Claim 29 words

The amplifying circuit of claim 4 further including means for generating the first and second control signals for maintaining a proportional relationship between the first and second tail currents.

Claim 7

Dependent Claim 92 words

The amplifying circuit of claim 4 wherein said means included in said means for supplying a first tail current is third current mirror amplifying means, having a first output circuit for supplying the first tail current, and having an input circuit to which the first control signal is applied; and said means included in said means for supplying a second tail current is fourth current mirror amplifying means having a first output circuit for supplying the second tail current and having an input circuit to which the second control signal is applied.

Claim 8

Dependent Claim 36 words

The amplifying circuit of claim 6 further comprising means connected between the respective input circuits of said third and fourth current mirror amplifying means for generating the first and second control signals by conducting current therebetween.

Claim 9

Dependent Claim 53 words

The amplifying circuit of claim 6 wherein one of said third and fourth current mirror amplifying means includes a further output circuit which connects to the input circuit of the other of said third and fourth current mirror amplifying means for applying the corresponding one of the first and second control signals thereto.

Claim 10

Dependent Claim 29 words

The amplifying circuit of claim 4 further including means for generating the first and second control signals for maintaining a complementary relationship between the first and second tail currents.

Claim 11

Dependent Claim 136 words

The amplifying circuit of claim 9 wherein said means included in said means for supplying a first tail current includes a further P-channel field-effect transistor having a drain electrode connected for supplying said first tail current, having a source electrode connected to said first supply terminal, and having a gate electrode; and wherein said means included in said means for supplying a second tail current includes a further N-channel field-effect transistor, having a drain electrode connected for supplying said second tail current, having a source electrode connected to said second supply terminal, and having a gate electrode; and wherein said means for generating the first and second control signals includes a control electrode for receiving a control potential thereat, and means connecting the respective gate electrodes of said N-channel and P-channel transistors to said control electrode.

Claim 12

Dependent Claim 55 words

The amplifying circuit of claim 10 wherein said control potential includes a fixed potential component, and a variable potential component, said fixed potential component tending to maintain the first and second tail currents at a quiescent level, and said variable potential component tending to vary said first and second tail currents in said complementary relationship.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1985-05-31	1985-11-30	1986-06-01	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1989-05-31	1989-11-30	1990-06-01	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1993-05-31	1993-11-30	1994-06-01	$7700.00	Window Closed / Lapsed

Operational amplifier employing complementary field-effect transistors

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