US5287070A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Balanced voltage comparator
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1992-09-02
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Granted: 1994-02-15
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Expires: 2012-09-02
Abstract
Abstract A biasing system for a CMOS differential comparator includes a unity gain amplifier for developing a reference voltage corresponding to the trip point of an output inverter. The reference voltage is applied to a voltage to current converter for developing a reference current proportional to the reference voltage. The reference current biases the output inverters at their trip points when the input voltages to the differential comparator are at the same potential. The biasing system includes a reference inverter having characteristics substantially identical to the output inverters. The output and input of the reference inverter are connected together so that a reference voltage is established at the inverter output which is always at the switch point of the inverter. A differential transistor stage includes resistive loads matched in process characteristics and sized to each pass one-half the value of the reference current to reduce the load capacitance at the differential stage. An output stage of the comparator circuit uses a source follower with characteristics matching those of the voltage to current converter so that the output nodes at the source follower have the same value as the reference voltage.
Inventors
- 👤 Bob Thelen
- 👤 Donald M. Bartlett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:22
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22; H03K5/24; H03K5/2472; H03K5/2481; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45179; H03F3/45183; H03F2203/00; H03F2203/45; H03F2203/45508; H03F2203/45674
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
144 words
A differential comparator circuit comprising: a constant current source; differential input means including at least a first and a second transistor having a commonly connected load current carrying terminal, each of said transistors further having a signal input terminal and another load current carrying terminal; current mirror means having a plurality of transistor mirror stages, at least one of said stages being coupled to said constant current source and another of said stages being coupled in circuit with said commonly connected load current carrying terminal of said differential input means; output transistor means having an output terminal coupled to another of said stages of said current mirror means and an input terminal coupled to said another load carrying terminal of one of said first and second transistors; and first and second resistors connected in series circuit arrangement with said first and second transistors, respectively.
Claim 2
Dependent Claim
144 words
A differential comparator circuit comprising: a constant current source; differential input means including at least a first and a second transistor having a commonly connected load current carrying terminal, each of said transistors further having a signal input terminal and another load current carrying terminal; current mirror means having a plurality of transistor mirror stages, at least one of said stages being coupled to said constant current source and another of said stages being coupled in circuit with said commonly connected load current carrying terminal of said differential input means; output transistor means having an output terminal coupled to another of said stages of said current mirror means and an input terminal coupled to said another load carrying terminal of one of said first and second transistors; and first and second resistors connected in series circuit arrangement with said first and second transistors, respectively.
Claim 3
Dependent Claim
48 words
The circuit of claim 1 and further including: another output transistor means having an output terminal coupled to yet another of said stages of said current mirror means and having an input terminal coupled to said another load carrying terminal of another of said first and second transistors.
Claim 4
Dependent Claim
116 words
The circuit of claim 1 wherein said constant current source comprises: a unity gain amplifier including a first inverter having an input terminal connected to an output terminal of said inverter; a bias amplifier having an input terminal coupled to said output terminal of said first inverter and having an output terminal for developing a voltage reference substantially equal to a voltage at said output terminal of said inverter; a reference current source comprising a series connected transistor and a bias resistor, said reference current source being coupled between a source of direct current electric power and said output terminal of said bias amplifier; and means coupling said reference current source to said current mirror means.
Claim 5
Dependent Claim
22 words
The circuit of claim 3 wherein said first and second resistors each have an ohmic resistance twice that of said bias resistor.
Claim 6
Dependent Claim
46 words
The circuit of claim 3 and further including a second inverter having an input terminal coupled to said output terminal of said output transistor means, said second inverter having matching characteristics with said first inverter such that said second inverter is biased at its trip point.
Claim 7
Dependent Claim
122 words
A CMOS integrated circuit differential comparator having improved response time comprising: an input differential circuit comprising at least a first and a second transistor each having a resistive load serially connected with a load current carrying terminal of each transistor; at least one source follower transistor having a gate terminal coupled to the load current carrying terminal of one of said first and second transistors; biasing means for setting a constant bias voltage at a source terminal of said source follower for establishing a constant gate-to-source voltage on said source follower; and means coupled in circuit with each of said input circuit and said source follower transistor for establishing a constant current through each of said circuit and said source follower transistor.
Claim 8
Dependent Claim
122 words
A CMOS integrated circuit differential comparator having improved response time comprising: an input differential circuit comprising at least a first and a second transistor each having a resistive load serially connected with a load current carrying terminal of each transistor; at least one source follower transistor having a gate terminal coupled to the load current carrying terminal of one of said first and second transistors; biasing means for setting a constant bias voltage at a source terminal of said source follower for establishing a constant gate-to-source voltage on said source follower; and means coupled in circuit with each of said input circuit and said source follower transistor for establishing a constant current through each of said circuit and said source follower transistor.
Claim 9
Dependent Claim
33 words
The comparator of claim 6 and including a first inverter connected to said source terminal of said source follower, said constant bias voltage being established at a trip point of said first inverter.
Claim 10
Dependent Claim
42 words
The comparator of claim 7 and including a bias circuit for setting said constant bias voltage, said bias circuit comprising a second inverter having an output terminal and an input terminal, said output and input terminals being coupled one to the other.
Claim 11
Dependent Claim
36 words
The comparator of claim 8 wherein said first inverter is selected to have matching characteristics with said second inverter for setting said bias voltage at said source follower to the trip point of said second inverter.
Claim 12
Dependent Claim
120 words
An integrated circuit differential comparator having improved response time comprising: an input differential circuit comprising at least a first and a second transistor each having a load serially connected with a load current carrying terminal of each transistor; at least one source follower transistor having a gate terminal coupled to the load current carrying terminal of one of said first and second transistors; biasing means for setting a constant bias voltage at a source terminal of said source follower for establishing a constant gate-to-source voltage on said source follower; and means coupled in circuit with each of said input circuit and said source follower transistor for establishing a constant current through each of said circuit and said source follower transistor.
Claim 13
Dependent Claim
120 words
An integrated circuit differential comparator having improved response time comprising: an input differential circuit comprising at least a first and a second transistor each having a load serially connected with a load current carrying terminal of each transistor; at least one source follower transistor having a gate terminal coupled to the load current carrying terminal of one of said first and second transistors; biasing means for setting a constant bias voltage at a source terminal of said source follower for establishing a constant gate-to-source voltage on said source follower; and means coupled in circuit with each of said input circuit and said source follower transistor for establishing a constant current through each of said circuit and said source follower transistor.
Claim 14
Dependent Claim
33 words
The comparator of claim 10 and including a first inverter connected to said source terminal of said source follower, said constant bias voltage being established at a trip point of said first inverter.
Claim 15
Dependent Claim
42 words
The comparator of claim 11 and including a bias circuit for setting said constant bias voltage, said bias circuit comprising a second inverter having an output terminal and an input terminal, said output and input terminals being coupled one to the other.
Claim 16
Dependent Claim
36 words
The comparator of claim 12 wherein said first inverter is selected to have matching characteristics with said second inverter for setting said bias voltage at said source follower to the trip point of said second inverter.
Claim 17
Independent Claim
83 words
A method for improving response time of a differential comparator, the comparator including a differential transistor stage having an output terminal coupled through a buffer stage to an output inverter, the method comprising the steps of: developing a reference voltage corresponding to a trip point of the output inverter; developing a reference current proportional to the reference voltage; biasing the output inverter at the trip point with the reference current; and maintaining a constant current through each of the comparator and buffer stage.
Claim 18
Independent Claim
83 words
A method for improving response time of a differential comparator, the comparator including a differential transistor stage having an output terminal coupled through a buffer stage to an output inverter, the method comprising the steps of: developing a reference voltage corresponding to a trip point of the output inverter; developing a reference current proportional to the reference voltage; biasing the output inverter at the trip point with the reference current; and maintaining a constant current through each of the comparator and buffer stage.
Claim 19
Dependent Claim
70 words
The method of claim 14 wherein the differential transistor stage includes at least two transistors, each transistor being coupled in circuit with a corresponding one of a pair of loads, the method comprising the further steps of: selecting the loads to have substantially matching process characteristics and resistive characteristics; and passing one-half of the reference current through each of the loads when the differential stage is in a balanced state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-14 | 1997-08-16 | 1998-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-14 | 2001-08-16 | 2002-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-14 | 2005-08-16 | 2006-02-15 | $7700.00 | Window Closed / Lapsed |