US4626713A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Trip-point clamping circuit for a semiconductor device
Assignee: STMicroelectronics lnc USA
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Filing: 1984-09-06
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Granted: 1986-12-02
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Expires: 2004-09-06
Abstract
Abstract A trip point clamping circuit for maintaining the voltage level at a node of connection to a sense arrangement including an inverter within defined bounds at the trip point of the inverter, the clamping circuit including a reference voltage, a source of similar current levels, a switch for turning the clamping circuit on and off, and a transistor responsive to the voltage level at said node of connection.
Inventors
- 👤 Robert D. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:12
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/003; H03K5/007; H03K17/00; H03K17/14; H03K17/145
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
158 words
A trip-point clamping circuit for a semiconductor device including an output node connected to a sensing device comprising inverter means for establishing a reference voltage level; current means for maintaining the same current level on each of a first and a second element output in the absence of a signal at said output node, first transistor means including a control gate coupled to the inverter means, a first current-carrying terminal coupled to the first current output and a second current carrying terminal, second transistor means for responding to the voltage level at said output node including a control gate coupled to the output node, a first current carrying terminal coupled to the output node and to the second current output and a second current-carrying terminal, and switch means supplied with current from the second current-carrying terminals of the first and second transistor means whereby the current to said switch means is varied by signals on said output node.
Claim 2
Dependent Claim
158 words
A trip-point clamping circuit for a semiconductor device including an output node connected to a sensing device comprising inverter means for establishing a reference voltage level; current means for maintaining the same current level on each of a first and a second element output in the absence of a signal at said output node, first transistor means including a control gate coupled to the inverter means, a first current-carrying terminal coupled to the first current output and a second current carrying terminal, second transistor means for responding to the voltage level at said output node including a control gate coupled to the output node, a first current carrying terminal coupled to the output node and to the second current output and a second current-carrying terminal, and switch means supplied with current from the second current-carrying terminals of the first and second transistor means whereby the current to said switch means is varied by signals on said output node.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-01 | 1990-06-02 | 1990-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-01 | 1994-06-02 | 1994-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-01 | 1998-06-02 | 1998-12-02 | $7700.00 | Window Closed / Lapsed |