Hysteresis circuit having a stable output free from noise superposed on input signal

Claim 2

A comparator comprising first and second input terminals, an output terminal, a first transistor having a control electrode connected to the first input terminal, a second transistor having a control electrode connected to the second input terminal, said first and second transistors being interconnected to form a differential amplifier, a first load connected to the first transistor, a second load connected to the second transistor, a phase-inverter, means for supplying an output of said differential amplifier to said phase-inverter, first switching means for establishing a first conduction path in parallel with said first load, said first switching means being controlled by an output of said phase-inverter, second switching means for establishing a second conduction path in parallel with said second load, said second switching means being controlled by an input to said phase-inverter, and means for coupling the output of said phase-inverter to said output terminal.

Claim 3

A comparator as claimed in claim 1, in which an input signal is applied to said first input terminal and a fixed voltage is applied to said second input terminal.

Claim 4

A comparator as claimed in claim 1, in which said first and second transistors are insulated gate field effect transistors, said first and second transistors being of one conductivity type, and said first and second switching means respectively include third and fourth insulated gate field effect transistors, said third and fourth transistors being of the opposite conductivity type.

Claim 5

A comparator as claimed in claim 3, in which said first load circuit includes a fifth insulated gate field effect transistor having a gate and drain connected in common, said second load circuit includes a sixth insulated gate field effect transistor having a gate connected to the gate of said fifth insulated gate field effect transistor, and said first and second conduction paths, respectively, include seventh and eighth insulated gate field effect transistors each having a gate connected to the gate of said fifth insulated gate field effect transistor.

Claim 6

A comparator comprising a differential amplifier supplied with an input signal voltage and a reference voltage, an output terminal, at least one amplifier stage for amplifying an output of said differential amplifier, a phase-inversion amplifier for inverting the phase of an output of said amplifier stage, means for applying an output of said phase-inversion amplifier to said output terminal, and circuit means including a feedback circuit from the input and the output of said phase-inversion amplifier to said differential amplifier for varying the gain of said differential amplifier each time the output signal condition at the output terminal varies.

Claim 7

A comparator comprising a differential amplifier supplied with an input signal voltage and a reference voltage, an output terminal, at least one amplifier stage for amplifying an output of said differential amplifier, a phase-inversion amplifier for inverting the phase of an output of said amplifier stage, means for applying an output of said phase-inversion amplifier to said output terminal, and circuit means including a feedback circuit from the input and the output of said phase-inversion amplifier to said differential amplifier for varying the gain of said differential amplifier each time the output signal condition at the output terminal varies.

Claim 8

A comparator as claimed in claim 5, in which said differential amplifier has a load circuit, and said feedback circuit includes a conduction path in parallel with said load circuit.

Claim 9

A comparator as claimed in claim 6, in which said differential amplifier includes a first transistor for receiving said input signal voltage and a second transistor for receiving said reference voltage, said load circuit includes a first load coupled to said first transistor and a second load coupled to said second transistor, said conduction path includes a first conduction path in parallel with said first load and a second conduction path in parallel to said second load, and said first and second conduction paths responding with the input and output of said phase-inversion amplifier for shunting a part of the current flowing through said load circuit.

Claim 10

A comparator comprising first and second input terminals, an output terminal; a first transistor having gate, drain, and source, said gate being connected to said first input terminal; a second transistor having gate, drain, and source, said gate connected to said second input terminal; said first and second transistors forming a differential amplifier circuit; a third transistor having gate, drain, and source, the drain-source path being connected in series with the drain-source path of said first transistor; a fourth transistor having gate, drain, and source, the drain-source path being connected in series with said drain-source path of the second transistor; the gate and drain of said third transistor and the gate of said fourth transistor being connected in common; a first circuit including fifth and sixth transistors each having gate, source and drain, said fifth and sixth transistors being connected in series with each other; a second circuit including seventh and eighth transistors each having gates and being connected in series with each other; said first circuit being connected in parallel with said third transistor, said second circuit being connected in parallel with said fourth transistor; the gates of said third, fifth and seventh transistors being connected in common; a ninth transistor having gate, source and drain, the gate being connected to the output of said differential amplifier circuit; and a phase-inversion amplifier having an input end connected to the drain of said ninth transistor, an output end of said phase-inversion amplifier being connected to said output terminal; the gate of said sixth transistor being connected to the output end of said phase-inversion amplifier, and the gate of said eighth transistor being connected to the input end of said phase-inversion amplifier.

Claim 11

A comparator comprising first and second input terminals, an output terminal; a first transistor having gate, drain, and source, said gate being connected to said first input terminal; a second transistor having gate, drain, and source, said gate connected to said second input terminal; said first and second transistors forming a differential amplifier circuit; a third transistor having gate, drain, and source, the drain-source path being connected in series with the drain-source path of said first transistor; a fourth transistor having gate, drain, and source, the drain-source path being connected in series with said drain-source path of the second transistor; the gate and drain of said third transistor and the gate of said fourth transistor being connected in common; a first circuit including fifth and sixth transistors each having gate, source and drain, said fifth and sixth transistors being connected in series with each other; a second circuit including seventh and eighth transistors each having gates and being connected in series with each other; said first circuit being connected in parallel with said third transistor, said second circuit being connected in parallel with said fourth transistor; the gates of said third, fifth and seventh transistors being connected in common; a ninth transistor having gate, source and drain, the gate being connected to the output of said differential amplifier circuit; and a phase-inversion amplifier having an input end connected to the drain of said ninth transistor, an output end of said phase-inversion amplifier being connected to said output terminal; the gate of said sixth transistor being connected to the output end of said phase-inversion amplifier, and the gate of said eighth transistor being connected to the input end of said phase-inversion amplifier.

Claim 12

A comparator as claimed in claim 8, in which said first to ninth transistors are insulated gate field effect transistors, the first and second transistors being of one conductivity type, and the third to ninth transistors being of the opposite conductivity type.

Claim 13

A comparator as claimed in claim 8, in which one of an input signal voltage and a reference voltage is applied to said first input terminal and the other is applied to said second input terminal.

Claim 14

A circuit comprising a differential amplifier having first and second sides and first and second variable impedance load circuit means respectively associated with and coupled to said first and second sides, an inverter circuit means having an input end and an output end, means for coupling said differential amplifier to the input end of said inverter circuit means, and a feedback circuit means for feeding a first feedback signal from the input end of said inverter circuit means to said first variable impedance load circuit means and a second feedback signal from the output end of said inverter circuit means to said second variable impedance load circuit means to vary the impedances of said first and second variable impedance load circuit means in response to voltage levels at the input and output ends of said inverter circuit.

Claim 15

A circuit comprising a differential amplifier having first and second sides and first and second variable impedance load circuit means respectively associated with and coupled to said first and second sides, an inverter circuit means having an input end and an output end, means for coupling said differential amplifier to the input end of said inverter circuit means, and a feedback circuit means for feeding a first feedback signal from the input end of said inverter circuit means to said first variable impedance load circuit means and a second feedback signal from the output end of said inverter circuit means to said second variable impedance load circuit means to vary the impedances of said first and second variable impedance load circuit means in response to voltage levels at the input and output ends of said inverter circuit.

Claim 16

The circuit of claim 11, wherein said first and second variable impedance load circuit means comprise first and second electronic switch means, respectively, said first and second electronic switch means being turned on or off alternatively responsive to said first and second feedback signals.

Claim 17

The circuit of claim 12, wherein said first variable impedance load circuit means further comprises first and second impedance means, said first electronic switch means and said first impedance means being coupled in series between both ends of said second impedance means, and said second variable impedance load circuit means further comprises third and fourth impedance means, said second electronic switch means and said third impedance means being coupled in series between both ends of said fourth impedance means.

Claim 18

The circuit of claim 12 wherein each of said first and second electronic switch means is a MOS device.

Claim 19

The circuit of claim 13 wherein each of said first and fourth impedance means is a MOS device.