Input stage for CMOS operational amplifier and method thereof

Claim 2

An input stage of an amplifier, comprising: a first transistor pair differentially coupled for receiving a differential input signal; a first current source coupled to common sources of said first transistor pair; a first transistor having a gate, a drain and a source, said source being coupled to said common sources of said first transistor pair, said drain being coupled to a first power supply conductor, said gate being coupled for receiving a first bias potential; a second transistor pair differentially coupled for receiving said differential input signal; a second current source coupled to common sources of said second transistor pair; a second transistor having a gate, a drain and a source, said source being coupled to said common sources of said second transistor pair, said drain being coupled to a second power supply conductor, said gate being coupled for receiving a second bias potential; and a first bias generator for generating said first bias potential, said first bias generator including, (a) a third transistor having a gate coupled for receiving a third bias potential, (b) a fourth transistor having a gate and a drain coupled together to said gate of said first transistor, (c) a fifth transistor having a drain coupled to sources of said third and fourth transistors, a source coupled to said second power supply conductor, and a gate coupled to a control input of said first current source, (d) a sixth transistor having a source coupled to said second power supply conductor, (e) a first resistor coupled between said gate of said fifth transistor and a gate of said sixth transistor, and (f) a current mirror having An input coupled to a drain of said sixth transistor, a first output coupled to a drain of said third transistor, and a second output coupled to said drain and said gate of said fourth transistor.

Claim 3

The input stage of an amplifier of claim 1, wherein said first transistor pair are n-channel transistors and said second transistor pair are p-channel transistors.

Claim 4

The input stage of the amplifier of claim 1, further including a second bias generator for generating said second bias potential.

Claim 5

The input stage of the amplifier of claim 3, wherein said first bias generator includes: a seventh transistor having a gate coupled to said gate of said fifth transistor, a drain coupled to said gate of said sixth transistor, and a source coupled to said second power supply conductor; and an eighth transistor having a drain coupled to said first power supply conductor, a gate coupled to said drain of said third transistor, and a source coupled to said gate of said fifth transistor.

Claim 6

The input stage of the amplifier of claim 4, wherein said current mirror circuit includes: a ninth transistor having a gate and drain being coupled together to said drain of said sixth transistor, and a source coupled to said first power supply conductor; a tenth transistor having a source coupled to said first power supply conductor, a gate coupled to said gate of said ninth transistor, and a drain coupled to said drain of said third transistor; and an eleventh transistor having a source coupled to said first power supply conductor, a gate coupled to said gate of said tenth transistor, and a drain coupled to said drain of said fourth transistor.

Claim 7

The input stage of the amplifier of claim 5, wherein said second bias generator includes: a twelfth transistor having a gate coupled for receiving a fourth bias potential, a drain, and a source; a thirteenth transistor having a gate, a drain coupled to said gate and to said gate of said second transistor, and a source coupled to said source of said twelfth transistor; a fourteenth transistor having a drain coupled to said source of said thirteenth transistor, a source coupled to said first power supply conductor, and a gate coupled to a control input of said second current source; a fifteenth transistor having a gate coupled to said gate of said fourteenth transistor, a drain, and a source coupled to said first power supply conductor; a sixteenth transistor having a drain, a source coupled to said second power supply conductor, and a gate coupled to said drain of said fifteenth transistor and to said gate of said fourteenth transistor; a second resistor coupled between said gate of said sixteenth transistor and said gate of said fourteenth transistor; a seventeenth transistor having a gate, a drain, and a source, said gate and drain being coupled together to said drain of said sixteenth transistor, said source coupled to said second power supply conductor; a eighteenth transistor having a source coupled to said second power supply conductor, a gate coupled to said gate of said seventeenth transistor, and a drain coupled to said drain of said twelfth transistor; a nineteenth transistor having a source coupled to said second power supply conductor, a gate coupled to said gate of said eighteenth transistor, and a drain coupled to said drain of said thirteenth transistor; and a twentieth transistor having a source coupled to said second power supply conductor, a gate coupled to said drain of said twelfth transistor, and a drain coupled to said gate of said fourteenth transistor.

Claim 8

The input stage of the amplifier of claim 6, wherein said twelfth, thirteenth, fourteenth, fifteenth, sixteenth, and twentieth transistors are p-channel transistors and said seventeenth, eighteenth, and nineteenth transistors are N-channel transistors.

Claim 9

An input stage of an amplifier, comprising: a first differential transistor pair coupled for receiving a differential input signal having a common mode voltage; first circuit means coupled to common sources of said first differential transistor pair for varying current flow through said first differential transistor pair in response to said common mode voltage of said differential input signal; a second differential transistor pair coupled for receiving said differential input signal; and second circuit means coupled to common sources of said second differential transistor pair for varying current flow through said second differential transistor pair in response to said common mode voltage of said differential input signal, said second circuit means varying current flow through said second differential transistor pair independent of said first circuit means varying current flow through said first differential transistor pair to maintain a constant transconductance for the amplifier.

Claim 10

An input stage of an amplifier, comprising: a first differential transistor pair coupled for receiving a differential input signal having a common mode voltage; first circuit means coupled to common sources of said first differential transistor pair for varying current flow through said first differential transistor pair in response to said common mode voltage of said differential input signal; a second differential transistor pair coupled for receiving said differential input signal; and second circuit means coupled to common sources of said second differential transistor pair for varying current flow through said second differential transistor pair in response to said common mode voltage of said differential input signal, said second circuit means varying current flow through said second differential transistor pair independent of said first circuit means varying current flow through said first differential transistor pair to maintain a constant transconductance for the amplifier.

Claim 11

The input stage of the amplifier of claim 8 , wherein said first and second circuit means includes: a first current source coupled to common sources of said first differential transistor pair; a first transistor having a gate, a drain and a source, said source being coupled to said common sources of said first differential transistor pair, said drain being coupled to a first power supply conductor, said gate being coupled for receiving a first bias potential; a second current source coupled to common sources of said second differential transistor pair; and a second transistor having a gate, a drain and a source, said source being coupled to said common sources of said second differential transistor pair, said drain being coupled to a second power supply conductor, said gate being coupled for receiving a second bias potential.

Claim 12

A circuit, comprising: a first transistor pair differentially coupled for receiving a differential input signal; first circuit means coupled to common sources of said first transistor pair for varying current flow through said first transistor pair to establish a first transconductance in response to a first control signal that is dependent on temperature and process variation; a second transistor pair differentially coupled for receiving said differential input signal; and second circuit means coupled to common sources of said second transistor pair for varying current flow through said second transistor pair to establish a second transconductance in response to a second control signal that is dependent on temperature and process variation where said second transconductance is matched to said first transconductance so that varying current flow through the second differential transistor pair is independent of the first circuit means varying current flow through the first transistor pair.

Claim 13

A circuit, comprising: a first transistor pair differentially coupled for receiving a differential input signal; first circuit means coupled to common sources of said first transistor pair for varying current flow through said first transistor pair to establish a first transconductance in response to a first control signal that is dependent on temperature and process variation; a second transistor pair differentially coupled for receiving said differential input signal; and second circuit means coupled to common sources of said second transistor pair for varying current flow through said second transistor pair to establish a second transconductance in response to a second control signal that is dependent on temperature and process variation where said second transconductance is matched to said first transconductance so that varying current flow through the second differential transistor pair is independent of the first circuit means varying current flow through the first transistor pair.

Claim 14

The circuit of claim 10, wherein said first circuit means includes: a first current source coupled to common sources of said first transistor pair; and a first transistor having a gate, a drain and a source, said source being coupled to said common sources of said first transistor pair, said drain being coupled to a first power supply conductor, said gate being coupled for receiving a first bias potential.

Claim 15

The circuit of claim 11, wherein said second circuit means includes: a second current source coupled to common sources of said second transistor pair; and a second transistor having a gate, a drain and a source, said source being coupled to said common sources of said second transistor pair, said drain being coupled to a second power supply conductor, said gate being coupled for receiving a second bias potential.

Claim 16

The circuit of claim 12, further including: a first bias generator for generating said first bias potential; and a second bias generator for generating said second bias potential.

Claim 17

The circuit of claim 13, wherein said first bias generator includes: a third transistor having a gate coupled for receiving a third bias potential, a drain, and a source; a fourth transistor having a gate, a drain coupled to said gate and to said gate of said first transistor, and a source coupled to said source of said third transistor; a fifth transistor having a drain coupled to said source of said fourth transistor, a source coupled to said second power supply conductor, and a gate coupled to a control input of said first current source; a sixth transistor having a gate coupled to said gate of said fifth transistor, a drain, and a source coupled to said second power supply conductor; a seventh transistor having a drain, a source coupled to said second power supply conductor, and a gate coupled to said drain of said sixth transistor and to said gate of said fifth transistor; a first resistor coupled between said gate of said seventh transistor and said gate of said fifth transistor; an eighth transistor having a gate, a drain, and a source, said gate and drain being coupled together to said drain of said seventh transistor, said source coupled to said first power supply conductor; a ninth transistor having a source coupled to said first power supply conductor, a gate coupled to said gate of said eighth transistor, and a drain coupled to said drain of said third transistor; a tenth transistor having a source coupled to said first power supply conductor, a gate coupled to said gate of said ninth transistor, and a drain coupled to said drain of said fourth transistor; and an eleventh transistor having a source coupled to said first power supply conductor, a gate coupled to said drain of said third transistor, and a drain coupled to said gate of said fifth transistor.

Claim 18

The circuit of claim 14, wherein said second bias generator includes: a twelfth transistor having a gate coupled for receiving a fourth bias potential, a drain, and a source; a thirteenth transistor having a gate, a drain coupled to said gate and to said gate of said second transistor, and a source coupled to said source of said twelfth transistor; a fourteenth transistor having a drain coupled to said source of said thirteenth transistor, a source coupled to said first power supply conductor, and a gate coupled to a control input of said second current source; a fifteenth transistor having a gate coupled to said gate of said fourteenth transistor, a drain, and a source coupled to said first power supply conductor; a sixteenth transistor having a drain, a source coupled to said first power supply conductor, and a gate coupled to said drain of said fifteenth transistor and to said gate of said fourteenth transistor; a second resistor coupled between said gate of said sixteenth transistor and said gate of said fourteenth transistor; a seventeenth transistor having a gate, a drain, and a source, said gate and drain being coupled together to said drain of said sixteenth transistor, said source coupled to said second power supply conductor; a eighteenth transistor having a source coupled to said second power supply conductor, a gate coupled to said gate of said seventeenth transistor, and a drain coupled to said drain of said twelfth transistor; a nineteenth transistor having a source coupled to said second power supply conductor, a gate coupled to said gate of said eighteenth transistor, and a drain coupled to said drain of said thirteenth transistor; and a twentieth transistor having a source coupled to said second power supply conductor, a gate coupled to said drain of said twelfth transistor, and a drain coupled to said gate of said fourteenth transistor.

Claim 19

The circuit of claim 15, wherein said first and second resistors are temperature and process dependent.

Claim 22

The method of claim 17, for varying current flow through said first transistor pair, further comprising the steps of: providing a first current source coupled to sources of said first transistor pair for sinking a first current; providing a first shunt transistor coupled to said sources of said first transistor pair; providing a first bias potential to said first shunt transistor to establish a first shunt current; and selecting the size of said first shunt transistor to provide said first shunt current that is three-fourths of said first current of said first current source when said common mode voltage equals said first bias potential.

Claim 23

The method of claim 18, for varying current flow through said second transistor pair, further comprising the steps of: providing a second current source coupled to sources of said second transistor pair for sinking a second current; providing a second shunt transistor coupled to said sources of said second transistor pair; providing a second bias potential to said second shunt transistor to establish a second shunt current; and selecting the size of said second shunt transistor to provide said second shunt current that is three-fourths of said second current of said second current source when said common mode voltage equals said second bias potential.