Combination driver-summing circuit for rail-to-rail differential amplifier

Claim 2

A differential amplifier with rail-to-rail common-mode range comprising: a positive supply voltage rail, a negative supply voltage rail, first and second amplifier input terminals for receiving a signal to be amplified, differential amplifier means comprising input means coupled to said first and second amplifier input terminals, output means, a first pair of transistors connected as a first differential amplifier to said positive supply voltage rail via a first current source, and a second pair of transistors connected as a second differential amplifier to said negative supply voltage rail via a second current source, a current summing circuit coupled to the output means of the differential amplifier means, a driver/output stage including first and second output transistors coupled to signal output terminal and having input means coupled to the current summing circuit, and a floating current source coupled to said summing circuit in a manner so as to control and to maintain a constant quiescent bias current in the output transistors.

Claim 3

A differential amplifier as claimed in claim 1 wherein said current summing circuit comprises a first current mirror circuit coupled between the positive supply voltage rail and a first terminal of the floating current source and a second current mirror circuit coupled between the negative supply voltage rail and a second terminal of the floating current source.

Claim 4

A differential amplifier as claimed in claim 2 wherein the driver/output stage comprises said first and second output transistors connected in series circuit between the positive and negative supply voltage rails and first and second bias control transistors connected in parallel between a first terminal of the first current mirror circuit and a first terminal of the second current mirror circuit, and means coupling a control electrode of the first output transistor to said first terminal of the first current mirror circuit and a control electrode of the second output transistor to the first terminal of the second current mirror circuit.

Claim 5

A differential amplifier as claimed in claim 3 wherein the source and drain of the first bias control transistor is connected to the drain and source, respectively, of the second bias control transistor.

Claim 6

A differential amplifier as claimed in claim 2 wherein the first current mirror circuit comprises first and second transistors having their control electrodes connected in common to a DC reference voltage and the second current mirror circuit comprises third and fourth transistors having their control electrodes connected in common to a further DC reference voltage.

Claim 7

A differential amplifier as claimed in claim 2 wherein the driver/output stage comprises first and second complementary bias control transistors connected in parallel between a first terminal of the first current mirror circuit and a first terminal of the second current mirror circuit, and said floating current source comprises third and fourth complementary transistors connected in parallel between said first and second terminals of the floating current source.

Claim 8

A differential amplifier as claimed in claim 1 wherein the driver/output stage comprises a current mirror circuit having a first circuit branch connected in series with a further current source between said positive and negative supply voltage rails and a second circuit branch connected in a second series circuit with at least one diode element between said positive and negative supply voltage rails.

Claim 9

A differential amplifier as claimed in claim 7 wherein said current summing circuit comprises a first current mirror circuit coupled between the positive supply voltage rail and a first terminal of the floating current source and a second current mirror circuit coupled between the negative supply voltage rail and a second terminal of the floating current source, and wherein the driver/output stage further comprises first and second complementary bias control transistors connected in parallel between a first terminal of the first current mirror circuit and a first terminal of the second current mirror circuit, and means coupling a control electrode of the first bias control transistor to a first junction point between the first circuit branch of the current mirror circuit and said further current source and coupling a control electrode of the second bias control transistor to a second junction point between the second circuit branch of the current mirror circuit and said one diode element.

Claim 10

A differential amplifier as claimed in claim 2 wherein the floating current source further comprises; first and second complementary transistors connected in parallel between said first and second terminals of the floating current source, a third transistor connected in series with a third current source to the positive supply voltage rail, a fourth transistor connected in series with a fourth current source to the negative supply voltage rail, and means coupling a control electrode of the first transistor and a control electrode of the second transistor to first and second junction points between the third transistor and third current source and between the fourth transistor and fourth current source, respectively.

Claim 11

A differential amplifier as claimed in claim 9 wherein the driver/output stage comprises first and second complementary bias control transistors connected in parallel between a first terminal of the first current mirror circuit and a first terminal of the second current mirror circuit.

Claim 12

A differential amplifier as claimed in claim 10 wherein the driver/output stage comprises said first and second output transistors connected in series circuit between the positive and negative supply voltage rails, and means coupling a control electrode of the first output transistor to said first terminal of the first current mirror circuit and a control electrode of the second output transistor to the first terminal of the second current mirror circuit.

Claim 13

A differential amplifier as claimed in claim 1 further comprising; a control transistor connected in series circuit with said first and second current sources between said positive and negative supply voltage rails and with a control electrode of the control transistor connected to a DC reference voltage.

Claim 14

A differential amplifier as claimed in claim 1 where the driver/output stage performs a biasing for class A-B operation.

Claim 15

A differential amplifier as claimed in claim 1 wherein the summing circuit comprises a folded cascode circuit arrangement.

Claim 16

A differential amplifier as claimed in claim 12, wherein the second current source comprises; a current mirror circuit having a first circuit branch coupling said second pair of transistors to the negative supply voltage rail and a second circuit branch connected in series circuit with the control transistor and the first current source between said positive and negative supply voltage rails.

Claim 17

A differential amplifier comprising: a positive supply voltage rail; a negative supply voltage rail, first and second amplifier input terminals for receiving a signal to be amplified, a rail-to-rail input stage comprising a first differential amplifier pair coupled to said positive supply voltage rail via a first current source, and a second complementary differential amplifier pair coupled to said negative supply voltage rail via a second current source, a current summing circuit, means coupling input means of the input stage to said first and second amplifier input terminals and output means of the input stage to the current summing circuit, a class AB biased driver/output stage including first and second complementary output transistors directly coupled to the current summing circuit and also coupled to signal output terminal of the differential amplifier, and a floating current source coupled to said summing circuit in a manner so as to control and to maintain a constant quiescent bias current in the output transistors whereby the quiescent bias current is independent of current conduction in the first and second differential amplifier pairs and of an input common-mode voltage.

Claim 18

A differential amplifier comprising: a positive supply voltage rail; a negative supply voltage rail, first and second amplifier input terminals for receiving a signal to be amplified, a rail-to-rail input stage comprising a first differential amplifier pair coupled to said positive supply voltage rail via a first current source, and a second complementary differential amplifier pair coupled to said negative supply voltage rail via a second current source, a current summing circuit, means coupling input means of the input stage to said first and second amplifier input terminals and output means of the input stage to the current summing circuit, a class AB biased driver/output stage including first and second complementary output transistors directly coupled to the current summing circuit and also coupled to signal output terminal of the differential amplifier, and a floating current source coupled to said summing circuit in a manner so as to control and to maintain a constant quiescent bias current in the output transistors whereby the quiescent bias current is independent of current conduction in the first and second differential amplifier pairs and of an input common-mode voltage.

Claim 19

A differential amplifier as claimed in claim 16 further comprising a control circuit coupled to the first and second complementary differential amplifier pairs for steering currents through same in a manner so as to maintain a gain of the input stage constant over a full range of a current-mode voltage of a signal to be amplified at the amplifier input terminals.