Semiconductor package including heat sink with layered conductive plate and non-conductive tape bonding to leads

Claim 2

A semiconductor package comprising: a semiconductor chip integrated with an electronic circuit; a heat sink having an upper surface on which the semiconductor chip is centrally attached by an epoxy resin layer coated on the upper surface, the heat sink being provided with an oxidation layer formed on the upper surface thereof; a plurality of leads attached to opposite lateral end portions of the upper surface of the heat sink by non-conductive bonding tapes, respectively, the leads extending laterally to a position outside of the package and serving to transmit signals from the semiconductor chip to the outside of the package; wires for electrically connecting the semiconductor chip to the leads, respectively; a plane comprised of a conductive thin plate and bonded between the heat sink and the leads at each lateral end portion of the heat sink by a non-conductive tape, said plate including wire bonding areas extending inwardly from said tape to provide a ground bonding area or a power bonding area; and a sealing resin molded on the semiconductor chip and peripheral elements thereof in order to protect them from external oxidation and erosion.

Claim 3

The semiconductor package in accordance with claim 1, wherein the plane has a multilayer plane structure consisting of a first conductive thin plate forming a ground bonding area, a second conductive thin plate forming a power bonding area, and a non-conductive tape interposed between the first and second conductive thin plates.

Claim 4

The semiconductor package in accordance with claim 1 or 2, wherein the conductive thin plate is a copper thin plate.

Claim 5

The semiconductor package in accordance with claim 1 or 2, wherein the non-conductive bonding tape is a polyimide tape.

Claim 6

A semiconductor package comprising: a semiconductor chip integrated with an electronic circuit; a heat sink having an upper surface on which the semiconductor chip is centrally attached by an epoxy resin layer coated on the upper surface, the heat sink being provided with an oxidation layer formed on the upper surface thereof; a plurality of leads attached to opposite lateral end portions of the upper surface of the heat sink by non-conductive bonding tapes, respectively, the leads serving to transmit signals from the semiconductor chip to the outside of the package; wires for electrically connecting the semiconductor chip to the leads respectively; a plane comprised of a conductive thin plate and bonded between the heat sink and the leads at each lateral end portion of the heat sink by a non-conductive tape to provide a ground bonding area or a power bonding area; a sealing resin molded on the semiconductor chip and peripheral elements thereof in order to protect them from external oxidation and erosion; and wherein the plane is formed with oxidation films on upper and lower surfaces thereof, respectively.

Claim 7

A semiconductor package comprising: a semiconductor chip integrated with an electronic circuit; a heat sink having an upper surface on which the semiconductor chip is centrally attached by an epoxy resin layer coated on the upper surface, the heat sink being provided with an oxidation layer formed on the upper surface thereof; a plurality of leads attached to opposite lateral end portions of the upper surface of the heat sink by non-conductive bonding tapes, respectively, the leads serving to transmit signals from the semiconductor chip to the outside of the package; wires for electrically connecting the semiconductor chip to the leads respectively; a plane comprised of a conductive thin plate and bonded between the heat sink and the leads at each lateral end portion of the heat sink by a non-conductive tape to provide a ground bonding area or a power bonding area; a sealing resin molded on the semiconductor chip and peripheral elements thereof in order to protect them from external oxidation and erosion; and wherein the plane is formed with oxidation films on upper and lower surfaces thereof, respectively.

Claim 8

The semiconductor package in accordance with claim 1 or 2, wherein the plane is plated with a silver layer on a portion of the upper surface thereof corresponding to a wire bonding region.

Claim 9

A semiconductor package comprising: a semiconductor chip integrated with an electronic circuit; a heat sink having an upper surface on which the semiconductor chip is centrally attached by an epoxy resin layer coated on the upper surface, the heat sink being provided with an oxidation layer formed on the upper surface thereof; a plurality of leads attached to opposite lateral end portions of the upper surface of the heat sink by non-conductive bonding tapes, respectively, serving to transmit signals from the semiconductor chip to the outside of the package; wires for electrically connecting the semiconductor chip to the leads, respectively; a plane comprised of a conductive thin plate and bonded between the heat sink and the leads at each lateral end portion of the heat sink by a non-conductive tape to provide a ground bonding area or a power bonding area; a sealing resin molded on the semiconductor chip and peripheral elements thereof in order to protect them from external oxidation and erosion; and wherein the plane is plated with a double layer consisting of a nickel layer and a palladium layer formed over the nickel layer on a portion of the upper surface thereof corresponding to a wire bonding region.

Claim 10

A semiconductor package comprising: a semiconductor chip integrated with an electronic circuit; a heat sink having an upper surface on which the semiconductor chip is centrally attached by an epoxy resin layer coated on the upper surface, the heat sink being provided with an oxidation layer formed on the upper surface thereof; a plurality of leads attached to opposite lateral end portions of the upper surface of the heat sink by non-conductive bonding tapes, respectively, serving to transmit signals from the semiconductor chip to the outside of the package; wires for electrically connecting the semiconductor chip to the leads, respectively; a plane comprised of a conductive thin plate and bonded between the heat sink and the leads at each lateral end portion of the heat sink by a non-conductive tape to provide a ground bonding area or a power bonding area; a sealing resin molded on the semiconductor chip and peripheral elements thereof in order to protect them from external oxidation and erosion; and wherein the plane is plated with a double layer consisting of a nickel layer and a palladium layer formed over the nickel layer on a portion of the upper surface thereof corresponding to a wire bonding region.

Claim 11

The semiconductor package in accordance with claim 7, wherein the nickel layer has a thickness relatively larger than that of the palladium layer.

Claim 12

A semiconductor package comprising: a semiconductor chip integrated with an electronic circuit; a heat sink having an upper surface on which the semiconductor chip is centrally attached by an epoxy resin layer coated on the upper surface, the heat sink being provided with an oxidation layer formed on the upper surface thereof; a plurality of leads attached to opposite lateral end portions of the upper surface of the heat sink by non-conductive bonding tapes, respectively, serving to transmit signals from the semiconductor chip to the outside of the package; wires for electrically connecting the semiconductor chip to the leads, respectively; a plane comprised of a conductive thin plate and bonded between the heat sink and the leads at each lateral end portion of the heat sink by a non-conductive tape to provide a ground bonding area or a power bonding area; a sealing resin molded on the semiconductor chip and peripheral elements thereof in order to protect them from external oxidation and erosion; and wherein the heat sink is plated with a nickel layer on a lower surface thereof.

Claim 13

A semiconductor package comprising: a semiconductor chip integrated with an electronic circuit; a heat sink having an upper surface on which the semiconductor chip is centrally attached by an epoxy resin layer coated on the upper surface, the heat sink being provided with an oxidation layer formed on the upper surface thereof; a plurality of leads attached to opposite lateral end portions of the upper surface of the heat sink by non-conductive bonding tapes, respectively, serving to transmit signals from the semiconductor chip to the outside of the package; wires for electrically connecting the semiconductor chip to the leads, respectively; a plane comprised of a conductive thin plate and bonded between the heat sink and the leads at each lateral end portion of the heat sink by a non-conductive tape to provide a ground bonding area or a power bonding area; a sealing resin molded on the semiconductor chip and peripheral elements thereof in order to protect them from external oxidation and erosion; and wherein the heat sink is plated with a nickel layer on a lower surface thereof.

Claim 14

The semiconductor package in accordance with claim 9, wherein a palladium layer is plated on the nickel layer.

Claim 15

The semiconductor package in accordance with claim 1 or 2, wherein the leads are in a welded connection to the plane.

Claim 16

a semiconductor package comprising: a semiconductor chip integrated with an electronic circuit; a heat sink having an upper surface on which the semiconductor chip is centrally attached by an epoxy resin layer coated on the upper surface; a plurality of leads attached to opposite lateral end portions of the upper surface of the heat sink by bonding tapes, respectively, the leads serving to transmit signals from the semiconductor chip to the outside of the package; wires for electrically connecting the semiconductor chip to the leads, respectively; a sealing resin molded on the semiconductor chip and peripheral elements thereof in order to protect them from external oxidation and erosion; and an oxidation layer formed on a portion of the upper surface of the heat sink to which the semiconductor chip is attached, and a silver layer plated on the remaining upper surface portion of the heat sink, whereby an easy ground bonding and power bonding can be achieved.

Claim 17

a semiconductor package comprising: a semiconductor chip integrated with an electronic circuit; a heat sink having an upper surface on which the semiconductor chip is centrally attached by an epoxy resin layer coated on the upper surface; a plurality of leads attached to opposite lateral end portions of the upper surface of the heat sink by bonding tapes, respectively, the leads serving to transmit signals from the semiconductor chip to the outside of the package; wires for electrically connecting the semiconductor chip to the leads, respectively; a sealing resin molded on the semiconductor chip and peripheral elements thereof in order to protect them from external oxidation and erosion; and an oxidation layer formed on a portion of the upper surface of the heat sink to which the semiconductor chip is attached, and a silver layer plated on the remaining upper surface portion of the heat sink, whereby an easy ground bonding and power bonding can be achieved.

Claim 18

The semiconductor package in accordance with claim 12, wherein a double layer consisting of a nickel layer and a palladium layer formed over the nickel layer is formed on the remaining upper surface portion of the heat sink, instead of the silver layer.

Claim 19

The semiconductor package in accordance with claim 12, wherein the nickel layer has a thickness relatively larger than the palladium layer.

Claim 20

The semiconductor package of claim 5 wherein the conductive thin plate is a copper thin plate.