Abstract An elemental titanium-free liner and cavity cleansing process is provided that allows for the elimination of conventional sputter etch and elemental titanium depositions. A low power plasma etch provides for pre-conditioning/cleansing of cavities such as contacts and vias. A refractory metal is provided as a cavity liner. Preferably, the liner is comprised of several discrete refractory metal liner layers, each having a thickness of about 25-100 Å, that can be applied by CVD and/or PVD. A low power plasma cleanse is preferably interposed between each liner layer deposition. A suitable metal plug can be deposited and directed into the cavity to complete cavity filling. Preferably, the metal plug is an elemental aluminum or aluminum alloy plug that is deposited by CVD and force-filled into the cavity to reduce the incidence of micro-voids within the cavity. Elimination of the conventional sputter etch and the high temperature processing (temp.≧.sup.˜ 400° C.) associated with such processing allows for the use of polymeric dielectrics, such as the family of polytetrafluorethylene ("PTFE") compounds, which exhibit a dielectric constant (κ) of about 1.9; parylene (κ=.sup.˜ 2.2-2.6); aerogels and xerogels (κ=.sup.˜ 1.1-1.8); and the family of polymeric spin-on-glass ("SOG") materials; use of all the foregoing materials being attractive because of the ability of these materials to reduce parasitic capacitance of the interconnects. Because these polymeric materials are temperature sensitive, their use has been limited, as conventional device fabrication practices typically require operation temperatures far in excess of the melting and/or decomposition temperature for these materials.
A method for depositing a liner in a cavity formed in a semiconductor device, comprising the steps of: providing a semiconductor substrate; forming a cavity in said substrate; and applying a refractory metal liner to said cavity, said liner comprising a plurality of discrete, titanium-free refractory metal liner layers applied to a thickness of up to about 100 Angstroms by at least one of a chemical vapor deposition and a physical vapor deposition process; and interposing a low power plasma cleanse of said cavity following deposition of said first liner layer.
Claim 2
Independent Claim
91 words
A method for depositing a liner in a cavity formed in a semiconductor device, comprising the steps of: providing a semiconductor substrate; forming a cavity in said substrate; and applying a refractory metal liner to said cavity, said liner comprising a plurality of discrete, titanium-free refractory metal liner layers applied to a thickness of up to about 100 Angstroms by at least one of a chemical vapor deposition and a physical vapor deposition process; and interposing a low power plasma cleanse of said cavity following deposition of said first liner layer.
Claim 3
Dependent Claim
21 words
The method according to claim 1, further comprising the step of depositing a fill metal in said cavity under positive pressure.
Claim 4
Dependent Claim
23 words
The method according to claim 1, wherein deposition of each of said liner layers is conducted at a temperature below about 400° C.
Claim 5
Dependent Claim
15 words
The method according to claim 1, wherein said substrate is comprised of a polymeric insulator.
Claim 6
Dependent Claim
20 words
The method according to claim 4, wherein said polymeric insulator comprises a dielectric having a dielectric constant below about 2.6.
Claim 7
Dependent Claim
26 words
The method according to claim 5, wherein said polymeric insulator is selected from the group consisting of polytetrafluoroethylene compounds, parylene, aerogels, xerogels and polymeric spin-on-glass materials.