US5472913A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating porous dielectric material with a passivation layer for electronics applications
Assignee: Texas Instruments Inc
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Filing: 1994-08-05
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Granted: 1995-12-05
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Expires: 2014-08-05
Abstract
Abstract A semiconductor device and process for making the same are disclosed which use porous dielectric materials to reduce capacitance between conductors, while allowing conventional photolithography and metal techniques and materials to be used in fabrication. In one structure, patterned conductors 18 are provided on an interlayer dielectric 10, with a substrate encapsulation layer 32 deposited conformally over this structure. A layer of porous dielectric material 22 (e.g. dried SiO2 gel) is then deposited to substantially fill the gaps between and also cover the conductors. A substantially solid cap layer 24 of a material such as SiO2 is then deposited, followed by a photolithography step to define via locations. Vias are etched through the cap layer, and then through the porous dielectric. A via passivating layer 30 is conformally deposited and then anisotropically etched to clear the bottom of the vias while leaving a passivating liner in the via, preventing the via metal from directly contacting the porous material. A second application of these steps may be used to form a second, overlying structure of patterned conductors 38, encapsulating layer 36, porous dielectric layer 40, and cap layer 42.
Inventors
- 👤 Robert H. Havemann
- 👤 Bruce E. Gnade
- 👤 Chih-Chen Cho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 07:28
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/66; H10P14/668; H10P14/6681; H10P14/6684; H10P14/6686; H10P14/65; H10P14/6502; H10P14/6506; H10P14/6516; H10P14/6529; H10P14/6534; H10P14/6546; H10P14/6548; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/072; H10W20/074; H10W20/076; H10W20/081; H10W20/40; H10W20/41; H10W20/425; H10W20/45; H10W20/46; H10W20/495; H10P14/63; H10P14/6326; H10P14/6342; H10P14/665; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
176 words
A method of integrating a porous dielectric layer into a semiconductor device, said method comprising: providing a layer of patterned conductors, formed on a substrate; filling spaces between and covering said conductors with a gel precursor solution; gelling said gel precursor solution to form a wet gel; drying said wet gel to form a porous dielectric layer, said porous dielectric layer having a porosity greater than about 50%; dehydroxylating said porous dielectric layer; depositing a substantially solid insulating cap layer over said porous dielectric layer; etching one or more vias through said cap layer; etching said vias through said porous dielectric layer; depositing a conformal via passivation layer over said cap layer and on exposed surfaces within said vias, said exposed surfaces including the bottoms and sidewalls of said vias; and anisotropically removing said passivation layer from bottoms of said vias, whereby a via having said passivation layer on said sidewalls is provided for completing electrical connections to said conductors, with said passivation layer and said cap layer separating said porous dielectric from said electrical connections.
Claim 2
Independent Claim
176 words
A method of integrating a porous dielectric layer into a semiconductor device, said method comprising: providing a layer of patterned conductors, formed on a substrate; filling spaces between and covering said conductors with a gel precursor solution; gelling said gel precursor solution to form a wet gel; drying said wet gel to form a porous dielectric layer, said porous dielectric layer having a porosity greater than about 50%; dehydroxylating said porous dielectric layer; depositing a substantially solid insulating cap layer over said porous dielectric layer; etching one or more vias through said cap layer; etching said vias through said porous dielectric layer; depositing a conformal via passivation layer over said cap layer and on exposed surfaces within said vias, said exposed surfaces including the bottoms and sidewalls of said vias; and anisotropically removing said passivation layer from bottoms of said vias, whereby a via having said passivation layer on said sidewalls is provided for completing electrical connections to said conductors, with said passivation layer and said cap layer separating said porous dielectric from said electrical connections.
Claim 3
Dependent Claim
56 words
The method of claim 1, further comprising: (a) depositing a substrate encapsulation layer conformally over exposed portions of said patterned conductors and said substrate, before said filling and covering step; and (b) removing said substrate encapsulation layer from said bottoms of said vias, as part of or after said removing of said via passivating layer step.
Claim 4
Dependent Claim
34 words
The method of claim 2, wherein said cap layer is comprised of at least two sublayers, with a top sublayer formed of a material substantially unaffected by the etch of said via passivation layer.
Claim 5
Dependent Claim
18 words
The method of claim 3, further comprising removing said top sublayer after said removal of said passivation layer.
Claim 6
Dependent Claim
14 words
The method of claim 3, wherein said top sublayer is composed of silicon nitride.
Claim 7
Dependent Claim
22 words
The method of claim 1, wherein said etching through said cap layer step uses said porous dielectric layer as an etch stop.
Claim 8
Dependent Claim
20 words
The method of claim 1, wherein said etching through said porous dielectric layer step uses a reactive ion etching technique.
Claim 9
Dependent Claim
39 words
The method of claim 1, wherein said removing step also removes portions of said passivation layer upon said cap layer and removes a top portion of said cap layer, while leaving a bottom portion of said cap layer intact.
Claim 10
Dependent Claim
31 words
The method of claim 1, wherein said dehydroxylating step comprises baking said device in a hydrogen-containing, substantially oxygen-free atmosphere, whereby hydroxyl groups are removed from pore surfaces of said porous dielectric.
Claim 11
Independent Claim
234 words
A method of integrating a porous dielectric layer into a semiconductor device, said method comprising: providing a layer of patterned conductors, formed on a substrate; depositing a substrate encapsulation layer conformally over exposed portions of said patterned conductors and said substrate; filling spaces between and covering said conductors with a gel precursor solution; gelling said gel precursor solution to form a wet gel; drying said wet gel to form a porous dielectric layer, the solid phase of said porous dielectric layer comprised substantially of silicon dioxide, said porous dielectric layer having a porosity greater than about 50%; baking said device in a hydrogen-containing, substantially oxygen-free atmosphere, whereby hydroxyl groups are removed from pore surfaces of said porous dielectric; depositing a substantially solid insulating cap layer over said porous dielectric layer; etching one or more vias through said cap layer; etching said vias through said porous dielectric layer; depositing a conformal via passivation layer over said cap layer and on exposed surfaces within said vias, said exposed surfaces including the bottoms and sidewalls of said vias; anisotropically removing said passivation layer from bottoms of said vias; and removing exposed portions of said substrate encapsulation layer from bottoms of said vias, whereby a via having said passivation layer on said sidewalls is provided for completing electrical connections to said conductors, with said passivation layer and said cap layer separating said porous dielectric from said electrical connections.
Claim 12
Independent Claim
234 words
A method of integrating a porous dielectric layer into a semiconductor device, said method comprising: providing a layer of patterned conductors, formed on a substrate; depositing a substrate encapsulation layer conformally over exposed portions of said patterned conductors and said substrate; filling spaces between and covering said conductors with a gel precursor solution; gelling said gel precursor solution to form a wet gel; drying said wet gel to form a porous dielectric layer, the solid phase of said porous dielectric layer comprised substantially of silicon dioxide, said porous dielectric layer having a porosity greater than about 50%; baking said device in a hydrogen-containing, substantially oxygen-free atmosphere, whereby hydroxyl groups are removed from pore surfaces of said porous dielectric; depositing a substantially solid insulating cap layer over said porous dielectric layer; etching one or more vias through said cap layer; etching said vias through said porous dielectric layer; depositing a conformal via passivation layer over said cap layer and on exposed surfaces within said vias, said exposed surfaces including the bottoms and sidewalls of said vias; anisotropically removing said passivation layer from bottoms of said vias; and removing exposed portions of said substrate encapsulation layer from bottoms of said vias, whereby a via having said passivation layer on said sidewalls is provided for completing electrical connections to said conductors, with said passivation layer and said cap layer separating said porous dielectric from said electrical connections.
Claim 13
Dependent Claim
22 words
The method of claim 10, wherein said etching through said cap layer step uses said porous dielectric layer as an etch stop.
Claim 14
Dependent Claim
18 words
The method of claim 1, said porosity of said porous dielectric layer having a value greater than 75%.
Claim 15
Dependent Claim
18 words
The method of claim 10, said porosity of said porous dielectric layer having a value greater than 75%.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-12-04 | 1999-06-05 | 1999-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-04 | 2003-06-05 | 2003-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-04 | 2007-06-05 | 2007-12-05 | $7700.00 | Window Closed / Lapsed |