← Back to Patent Explorer
US5841196A Expired / Lapsed US ⏱️ 0.0 years remaining

Fluted via formation for superior metal step coverage

Assignee: Advanced Micro Devices Inc
•
Filing: 1997-11-14
•
Granted: 1998-11-24
•
Expires: 2017-11-14
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method of forming a via in a interlevel dielectric of a semiconductor device wherein the via has a fluted sidewall. A semiconductor substrate is provided having a first conductive layer formed thereon. A dielectric layer is then formed on the first conductive layer. A photoresist layer is deposited on a dielectric layer and a contact opening is formed in the photoresist layer to expose a contact region of the dielectric layer. A first etch step is performed to remove portions of the dielectric layer proximal to the contact region to form a first stage of the fluted via. The first stage includes a first sidewall stage extending from an upper surface of the dielectric layer at an angle less than 50°. The first stage of the fluted via exterds a first lateral distance which is greater than a lateral dimension of the contact opening. A second etch step is then performed to further remove portions of the dielectric layer to form a second stage of the fluted via. The second stage includes a second sidewall stage extending from the first sidewall stage at a second angle between 40° and 70°. A third etch step is then performed to further remove portions of the dielectric layer to form a third and final. stage of the fluted via. The fluted via extends from an upper surface of the dielectric layer to an upper surface of the first conductive layer. The third stage includes a third stage sidewall extending from said second stage side wall to said upper surface of said first conductive layer at an angle between 60° and 80°.

Inventors

  • 👤 Subhash Gupta
  • 👤 Robert Flores
  • 👤 Michael Ross Stamm
  • 👤 Eric Thomas Sharp
  • 👤 Erich W. E. Denninger
  • 👤 Pamela G. Dye
  • 👤 Joel Samuel Utz
  • 👤 James K. Kai

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 00:14
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082; H10W20/40; H10W20/41; H10W20/42

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 188 words
In a semiconductor device, an interlevel contact structure comprising: a first conductive layer formed on an upper surface of a semiconductor substrate; an interlevel dielectric layer formed on said first conductive layer wherein said interlevel dielectric layer includes a fluted via defined by an annular sidewall of said dielectric layer wherein said annular sidewall extends from an upper surface of said dielectric layer to an upper layer of said first conductive layer and wherein said annular sidewall includes a first stage sidewall extending from said upper surface of said dielectric layer to a second sidewall stage of said annular sidewall at an angle of less than 50° and further wherein said second sidewall stage extends from said first sidewall stage to a third sidewall stage at an angle of between 40° and 70° and wherein said third sidewall stage extends from said second sidewall stage to an upper surface of said first conductive layer at an angle of between 60° and 80°; and a second conductive layer formed on said inter-level dielectric and within said fluted via such that said second conductive layer contacts said first conductive layer.
Claim 2
Dependent Claim 188 words
In a semiconductor device, an interlevel contact structure comprising: a first conductive layer formed on an upper surface of a semiconductor substrate; an interlevel dielectric layer formed on said first conductive layer wherein said interlevel dielectric layer includes a fluted via defined by an annular sidewall of said dielectric layer wherein said annular sidewall extends from an upper surface of said dielectric layer to an upper layer of said first conductive layer and wherein said annular sidewall includes a first stage sidewall extending from said upper surface of said dielectric layer to a second sidewall stage of said annular sidewall at an angle of less than 50° and further wherein said second sidewall stage extends from said first sidewall stage to a third sidewall stage at an angle of between 40° and 70° and wherein said third sidewall stage extends from said second sidewall stage to an upper surface of said first conductive layer at an angle of between 60° and 80°; and a second conductive layer formed on said inter-level dielectric and within said fluted via such that said second conductive layer contacts said first conductive layer.
Claim 3
Dependent Claim 26 words
The contact structure of claim 1 wherein said first conductive layer comprises a material selected from the group consisting heavily doped polysilicon and an aluminum alloy.
Claim 4
Dependent Claim 15 words
The contact structure of claim 1 wherein said second conductive layer comprises an aluminum alloy.
Claim 5
Dependent Claim 15 words
The contact structure of claim 1 wherein said dielectric layer comprises a deposited oxide material.
Claim 6
Dependent Claim 27 words
The contact structure of claim 1 wherein the step coverage of the second conductive layer in said fluted via is approximately equal to or greater than 30%.

References Cited (Backward Citations)

US3986912A Cited
US4354897A Cited
US4484978A Cited
US4729815A Cited
US4857141A Cited
US4978420A Cited
US5591675A Cited
US5453403A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-11-23 2002-05-25 2002-11-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-11-23 2006-05-25 2006-11-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-11-23 2010-05-25 2010-11-24 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag