US4857141A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming holes in semiconductor integrated circuit device
Assignee: Toshiba Corp
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Filing: 1988-04-13
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Granted: 1989-08-15
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Expires: 2008-04-13
Abstract
Abstract A recess is formed in the surface area of a layer-insulation film by an isotropic etching process, and a hole is formed in the recess by a first anisotropic etching process. After this, a second anisotropic etching process is effected to taper the hole to remove an edge portion at the opening of the recess, the boundary portion between the recess and the side wall formed by the anisotropic etching process, and the vertical side wall of the hole. A wiring metal layer is formed on part of the layer-insulation film and in the hole.
Inventors
- 👤 Masahiro Abe
- 👤 Yasukazu Mase
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:11
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
96 words
A hole forming method for semiconductor integrated circuit device comprising the steps of: forming an insulation layer on a conductive layer; forming a recess in the surface area of said insulation layer on said conductive layer by an isotropic etching process; forming a hole in said recess to reach said conductive layer by a first anisotropic etching process, said hole being narrow in width than said recess; effecting a second anisotropic etching process to taper said recess and said hole; and forming a metal wiring layer on part of said insulation layer and in said hole.
Claim 2
Dependent Claim
96 words
A hole forming method for semiconductor integrated circuit device comprising the steps of: forming an insulation layer on a conductive layer; forming a recess in the surface area of said insulation layer on said conductive layer by an isotropic etching process; forming a hole in said recess to reach said conductive layer by a first anisotropic etching process, said hole being narrow in width than said recess; effecting a second anisotropic etching process to taper said recess and said hole; and forming a metal wiring layer on part of said insulation layer and in said hole.
Claim 3
Dependent Claim
37 words
A hole forming method according to claim 1, wherein said conductive layer includes at least one diffusion region of a first conductivity type formed in the surface area of the semiconductor substrate of a second conductivity type.
Claim 4
Dependent Claim
18 words
A hole forming method according to claim 2, wherein said diffusion region is used as a wiring layer.
Claim 5
Dependent Claim
25 words
A hole forming method according to claim 2, wherein said diffusion region is part of constituents of an semiconductor element formed in said semiconductor substrate.
Claim 6
Dependent Claim
29 words
A hole forming method according to claim 1, wherein said conductive layer includes a conductive metal layer formed on an insulation film which is formed on said semiconductor substrate.
Claim 7
Dependent Claim
28 words
A hole forming method according to claim 4, wherein said conductive metal layer is formed a conductive material selected from a group consisting of Al, Al-Si, and Al-Si-Cu.
Claim 8
Dependent Claim
17 words
A hole forming method according to claim 1, wherein said insulation film includes a CVD-SiO 2 film.
Claim 9
Dependent Claim
29 words
A hole forming method according to claim 1, wherein said isotropic etching process and first anisotropic etching process are effected with the same resist pattern used as a mask.
Claim 10
Dependent Claim
22 words
A hole forming method according to claim 1, wherein each of said first and second anisotropic etching processes is an RIE process.
Claim 11
Dependent Claim
35 words
A hole forming method according to claim 1, wherein the depth of said recess formed in said insulation layer by the isotropic etching process is set to substantially one third thickness of said insulation layer.
Claim 12
Dependent Claim
27 words
A hole forming method according to claim 1, wherein said metal wiring layer is formed by patterning a metal layer which is formed by a sputtering method.
Claim 13
Dependent Claim
29 words
A hole forming method according to claim 11, wherein said metal wiring layer is formed of a conductive material selected from a group consisting of Al, Al-Si, and Al-Si-Cu.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-14 | 1993-02-13 | 1993-08-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-14 | 1997-02-13 | 1997-08-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-14 | 2001-02-13 | 2001-08-15 | $7700.00 | Window Closed / Lapsed |