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US5838582A
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US
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Method and system for performing parasitic capacitance estimations on interconnect data within an integrated circuit
Assignee: International Business Machines Corp
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Filing: 1996-10-07
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Granted: 1998-11-17
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Expires: 2016-10-07
Abstract
Abstract A method and system for providing parasitic capacitance estimation on interconnect data for an integrated circuit is disclosed. An integrated circuit typically includes a substrate layer and several metal layers. In accordance with the method and system of the present invention, a center wire within one of the several metal layers is first identified. Then, a first capacitance value between a first wire and the center wire as well as a second capacitance value between a second wire and the center wire are determined. The first wire, the second wire, and the center wire are in the same metal layer. Next, a third capacitance value between a third wire and the center wire is determined. This third wire is in a metal layer located directly beneath the center wire. Finally, a fourth capacitance value between a fourth wire and the center wire is determined. The fourth wire is in a metal layer located directly above the center wire. If there are more than one wire within the metal layer directly above the center wire, the fourth capacitance value is distributed among all these wires. By so doing, the total parasitic capacitance for the center wire can be estimated by utilizing the first capacitance value, the second capacitance value, the third capacitance value, and the fourth capacitance value or the distributed fourth capacitance values.
Inventors
- 👤 Sharad Mehrotra
- 👤 Paul Gerard Villarrubia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 23:48
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
227 words
A method of performing parasitic capacitance estimation on interconnect data for an integrated circuit, wherein said integrated circuit includes a substrate layer and a plurality of metal layers, said method comprising the steps of: identifying a center wire within one of said plurality of metal layers; determining a first capacitance value between a first wire and said center wire, wherein said first wire and said center wire are in the same metal layer of said plurality of metal layers; determining a second capacitance value between a second wire and said center wire, wherein said second wire and said center wire are in the same metal layer of said plurality of metal layers; determining a third capacitance value between a third wire and said center wire, wherein said third wire is in a metal layer directly beneath said center wire; determining a fourth capacitance value between a fourth wire and said center wire, wherein said fourth wire is in a metal layer directly above said center wire; distributing said fourth capacitance value among a plurality of wires if there is more than one wire within said metal layer directly above said center wire; and estimating a total parasitic capacitance for said center wire based on said first capacitance value, said second capacitance value, said third capacitance value, and said fourth capacitance value or said distributed fourth capacitance values.
Claim 2
Independent Claim
227 words
A method of performing parasitic capacitance estimation on interconnect data for an integrated circuit, wherein said integrated circuit includes a substrate layer and a plurality of metal layers, said method comprising the steps of: identifying a center wire within one of said plurality of metal layers; determining a first capacitance value between a first wire and said center wire, wherein said first wire and said center wire are in the same metal layer of said plurality of metal layers; determining a second capacitance value between a second wire and said center wire, wherein said second wire and said center wire are in the same metal layer of said plurality of metal layers; determining a third capacitance value between a third wire and said center wire, wherein said third wire is in a metal layer directly beneath said center wire; determining a fourth capacitance value between a fourth wire and said center wire, wherein said fourth wire is in a metal layer directly above said center wire; distributing said fourth capacitance value among a plurality of wires if there is more than one wire within said metal layer directly above said center wire; and estimating a total parasitic capacitance for said center wire based on said first capacitance value, said second capacitance value, said third capacitance value, and said fourth capacitance value or said distributed fourth capacitance values.
Claim 3
Dependent Claim
49 words
The method of performing parasitic capacitance estimation on interconnect data within an integrated circuit according to claim 1, wherein said step of distributing further includes a step of distributing said fourth capacitance value according to a horizontal distance from each of said plurality of wires to said center wire.
Claim 4
Dependent Claim
52 words
The method of performing parasitic capacitance estimation on interconnect data within an integrated circuit according to claim 1, wherein said method further includes a step of distributing said fourth capacitance value according to a contributing function of any fringing wire and an imaginary fourth wire if said fourth wire is not present.
Claim 5
Dependent Claim
44 words
The method of performing parasitic capacitance estimation on interconnect data within an integrated circuit according to claim 1, wherein said first wire is adjacent to the left of said center wire while said second wire is adjacent to the right of said center wire.
Claim 6
Dependent Claim
38 words
The method of performing parasitic capacitance estimation on interconnect data within an integrated circuit according to claim 1, wherein said third wire is directly beneath said center wire while said fourth wire is directly above said center wire.
Claim 7
Dependent Claim
240 words
A computer system for performing parasitic capacitance estimation on interconnect data for an integrated circuit, wherein said integrated circuit includes a substrate layer and a plurality of metal layers, said computer system comprising: means for identifying a center wire within one of said plurality of metal layers; means for determining a first capacitance value between a first wire and said center wire, wherein said first wire and said center wire are in the same metal layer of said plurality of metal layers; means for determining a second capacitance value between a second wire and said center wire, wherein said second wire and said center wire are in the same metal layer of said plurality of metal layers; means for determining a third capacitance value between a third wire and said center wire, wherein said third wire is in a metal layer directly beneath said center wire; means for determining a fourth capacitance value between a fourth wire and said center wire, wherein said fourth wire is in a metal layer directly above said center wire; means for distributing said fourth capacitance value among a plurality of wires if there is more than one wire within said metal layer directly above said center wire; and means for estimating a total parasitic capacitance for said center wire based on said first capacitance value, said second capacitance value, said third capacitance value and said fourth capacitance value or said distributed fourth capacitance values.
Claim 8
Dependent Claim
240 words
A computer system for performing parasitic capacitance estimation on interconnect data for an integrated circuit, wherein said integrated circuit includes a substrate layer and a plurality of metal layers, said computer system comprising: means for identifying a center wire within one of said plurality of metal layers; means for determining a first capacitance value between a first wire and said center wire, wherein said first wire and said center wire are in the same metal layer of said plurality of metal layers; means for determining a second capacitance value between a second wire and said center wire, wherein said second wire and said center wire are in the same metal layer of said plurality of metal layers; means for determining a third capacitance value between a third wire and said center wire, wherein said third wire is in a metal layer directly beneath said center wire; means for determining a fourth capacitance value between a fourth wire and said center wire, wherein said fourth wire is in a metal layer directly above said center wire; means for distributing said fourth capacitance value among a plurality of wires if there is more than one wire within said metal layer directly above said center wire; and means for estimating a total parasitic capacitance for said center wire based on said first capacitance value, said second capacitance value, said third capacitance value and said fourth capacitance value or said distributed fourth capacitance values.
Claim 9
Dependent Claim
50 words
The computer system for performing parasitic capacitance estimation on interconnect data for an integrated circuit according to claim 6, wherein said means for distributing further includes a means for distributing said fourth capacitance value according to a horizontal distance from each of said plurality of wires to said center wire.
Claim 10
Dependent Claim
54 words
The computer system for performing parasitic capacitance estimation on interconnect data for an integrated circuit according to claim 6, wherein said computer system further includes a means for distributing said fourth capacitance value according to a contributing function of any fringing wire and an imaginary fourth wire if said fourth wire is not present.
Claim 11
Dependent Claim
45 words
The computer system for performing parasitic capacitance estimation on interconnect data for an integrated circuit according to claim 6, wherein said first wire is adjacent to the left of said center wire while said second wire is adjacent to the right of said center wire.
Claim 12
Dependent Claim
39 words
The computer system for performing parasitic capacitance estimation on interconnect data for an integrated circuit according to claim 6, wherein said third wire is directly beneath said center wire while said fourth wire is directly above said center wire.
Claim 13
Dependent Claim
256 words
A computer program product for performing parasitic capacitance estimation on interconnect data for an integrated circuit, wherein said integrated circuit includes a substrate layer and a plurality of metal layers, said computer program product comprising: program code means for identifying a center wire within one of said plurality of metal layers; program code means for determining a first capacitance value between a first wire and said center wire, wherein said first wire and said center wire are in the same metal layer of said plurality of metal layers; program code means for determining a second capacitance value between a second wire and said center wire, wherein said second wire and said center wire are in the same metal layer of said plurality of metal layers; program code means for determining a third capacitance value between a third wire and said center wire, wherein said third wire is in a metal layer directly beneath said center wire; program code means for determining a fourth capacitance value between a fourth wire and said center wire, wherein said fourth wire is in a metal layer directly above said center wire; program code means for distributing said fourth capacitance value among a plurality of wires if there is more than one wire within said metal layer directly above said center wire; and program code means for estimating a total parasitic capacitance for said center wire based on said first capacitance value, said second capacitance value, said third capacitance value and said fourth capacitance value or said distributed fourth capacitance values.
Claim 14
Dependent Claim
256 words
A computer program product for performing parasitic capacitance estimation on interconnect data for an integrated circuit, wherein said integrated circuit includes a substrate layer and a plurality of metal layers, said computer program product comprising: program code means for identifying a center wire within one of said plurality of metal layers; program code means for determining a first capacitance value between a first wire and said center wire, wherein said first wire and said center wire are in the same metal layer of said plurality of metal layers; program code means for determining a second capacitance value between a second wire and said center wire, wherein said second wire and said center wire are in the same metal layer of said plurality of metal layers; program code means for determining a third capacitance value between a third wire and said center wire, wherein said third wire is in a metal layer directly beneath said center wire; program code means for determining a fourth capacitance value between a fourth wire and said center wire, wherein said fourth wire is in a metal layer directly above said center wire; program code means for distributing said fourth capacitance value among a plurality of wires if there is more than one wire within said metal layer directly above said center wire; and program code means for estimating a total parasitic capacitance for said center wire based on said first capacitance value, said second capacitance value, said third capacitance value and said fourth capacitance value or said distributed fourth capacitance values.
Claim 15
Dependent Claim
55 words
The computer program product for performing parasitic capacitance estimation on interconnect data for an integrated circuit according to claim 11, wherein said program code means for distributing further includes a program code means for distributing said fourth capacitance value according to a horizontal distance from each of said plurality of wires to said center wire.
Claim 16
Dependent Claim
58 words
The computer program product for performing parasitic capacitance estimation on interconnect data for an integrated circuit according to claim 11, wherein said computer program product further includes a program code means for distributing said fourth capacitance value according to a contributing function of any fringing wire and an imaginary fourth wire if said fourth wire is not present.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-16 | 2002-05-18 | 2002-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-16 | 2006-05-18 | 2006-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-16 | 2010-05-18 | 2010-11-17 | $7700.00 | Window Closed / Lapsed |