US5367469A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Predictive capacitance layout method for integrated circuits
Assignee: Philips Semiconductors Inc
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Filing: 1990-12-13
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Granted: 1994-11-22
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Expires: 2010-12-13
Abstract
Abstract A method for designing a circuit layout which includes the steps of supplying a predictive capacitance value for at least one net of a circuit layout, and placing and routing all nets of the circuit layout using at least one predictive capacitance value as a layout design constraint.
Inventors
- 👤 Mark R. Hartoog
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 00:12
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/39; G06F30/392; G06F30/394
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
134 words
A method for designing circuit layouts, including simulating a circuit on a computer, comprising the steps of: supplying a predictive capacitance value to the computer for at least one net of a circuit layout by calculating an average capacitance per unit wire length for the circuit layout and converting, via the average capacitance per unit wire length, the predictive capacitance for the at least one net of the circuit layout into a maximum wire length value for use as the layout design constraint; using the estimated wire length value in the computer for predicting the performance of the circuit prior to the layout; placing and routing all nets of the circuit layout on the simulated circuit using the at least one predictive capacitance value as a layout design constraint during the placing and routing.
Claim 2
Independent Claim
134 words
A method for designing circuit layouts, including simulating a circuit on a computer, comprising the steps of: supplying a predictive capacitance value to the computer for at least one net of a circuit layout by calculating an average capacitance per unit wire length for the circuit layout and converting, via the average capacitance per unit wire length, the predictive capacitance for the at least one net of the circuit layout into a maximum wire length value for use as the layout design constraint; using the estimated wire length value in the computer for predicting the performance of the circuit prior to the layout; placing and routing all nets of the circuit layout on the simulated circuit using the at least one predictive capacitance value as a layout design constraint during the placing and routing.
Claim 3
Dependent Claim
32 words
The method of claim 1, wherein the step of supplying includes the step of: statistically determining predictive capacitances for different types of circuit nets based on at least one prior circuit design.
Claim 4
Dependent Claim
31 words
The method of claim 1, wherein predictive capacitance values are supplied for all nets of the circuit layout, and all of the predictive capacitance values are used as layout design constraints.
Claim 5
Dependent Claim
33 words
The method of claim 3, wherein the step of supplying includes the step of statistically determining predictive capacitance values for different types of circuit nets based on at least one prior circuit design.
Claim 6
Dependent Claim
47 words
The method of claim 4, wherein the step of supplying further includes the step of: converting, via the average capacitance per unit wire length, the predictive capacitances for all nets of the circuit layout into maximum wire length values for use as the layout design constraints, respectively.
Claim 7
Dependent Claim
65 words
The method of claim 4, wherein the step of placing and routing further includes steps of: estimating a capacitance value for each net placed in the circuit layout; comparing the estimated capacitance for each net placed in the circuit layout with the statistically determined predictive capacitance for that net; and minimizing the number of nets whose estimated capacitance exceeds their respective statistically determined predictive capacitance.
Claim 8
Dependent Claim
15 words
The method of claim 6, wherein the step of minimizing uses a cost evaluation function.
Claim 9
Dependent Claim
65 words
The method of claim 6, wherein the step of minimizing includes the steps of: assigning first weights to nets whose estimated capacitance exceeds their statistically determined predictive capacitance; assigning second weights, lower than the first weights, to nets whose estimated capacitance is less than their statistically determined predictive capacitance; and, locating the nets in the circuit layout, with nets assigned the first weights receiving priority.
Claim 10
Dependent Claim
37 words
The method of claim 8, wherein the steps of comparing and minimizing are repeated until all nets have been placed and routed in the circuit layout, and a cost function value for the circuit layout is minimized.
Claim 11
Dependent Claim
39 words
The method according to claim 9, wherein the cost function value reflects the number of nets whose estimated capacitance exceeds their respective statistically determined predictive capacitance and the magnitude by which the statistically determined predictive capacitance has been exceeded.
Claim 12
Dependent Claim
59 words
The method according to claim 10, wherein the statistically determined predictive capacitances and the estimated capacitances are formed as statistically determined wire lengths and estimated wire lengths, respectively, the statistically determined wire lengths and the estimated wire lengths being used in place of the statistically determined predictive capacitances and the estimated capacitances during the steps of comparing and minimizing.
Claim 13
Dependent Claim
15 words
The method of claim 1, wherein the circuit layout is a standard cell integrated circuit.
Claim 14
Dependent Claim
15 words
The method of claim 1, wherein the circuit layout is a gate array integrated circuit.
Claim 15
Independent Claim
196 words
A method for designing an integrated circuit layout, including simulating an integrated circuit on a computer, comprising the steps of: statistically determining a predictive interconnect capacitance for different types of integrated circuit layout nets; on the computer, calculating an average capacitance per unit wire length for the integrated circuit layout; on the computer, converting the predictive interconnect capacitance for each different type of net into a maximum wire length value using the calculated average capacitance; placing at least one net at a desired location in an integrated circuit layout design on the simulated integrated circuit, and estimating wire length of each net on the basis of the placement; on the computer, comparing the estimated wire length of each net with the maximum wire length for that net; on the computer, assigning first weights to nets whose estimated wire length value exceeds its maximum wire length value and assigning second weights, lower than the first weights, to nets whose estimated wire length value is less than its maximum wire length value; and, repeating the steps of placing, comparing and assigning until all nets have been placed in the integrated circuit layout design on the simulated integrated circuit.
Claim 16
Independent Claim
196 words
A method for designing an integrated circuit layout, including simulating an integrated circuit on a computer, comprising the steps of: statistically determining a predictive interconnect capacitance for different types of integrated circuit layout nets; on the computer, calculating an average capacitance per unit wire length for the integrated circuit layout; on the computer, converting the predictive interconnect capacitance for each different type of net into a maximum wire length value using the calculated average capacitance; placing at least one net at a desired location in an integrated circuit layout design on the simulated integrated circuit, and estimating wire length of each net on the basis of the placement; on the computer, comparing the estimated wire length of each net with the maximum wire length for that net; on the computer, assigning first weights to nets whose estimated wire length value exceeds its maximum wire length value and assigning second weights, lower than the first weights, to nets whose estimated wire length value is less than its maximum wire length value; and, repeating the steps of placing, comparing and assigning until all nets have been placed in the integrated circuit layout design on the simulated integrated circuit.
Claim 17
Dependent Claim
170 words
A computer implemented method for designing an integrated circuit layout comprising the computer implemented steps of: statistically determining a predictive interconnect capacitance for different types of integrated circuit layout nets; calculating an average capacitance per unit wire length for the integrated circuit layout; converting the predictive interconnect capacitance for each different type of net into a maximum wire length value using the calculated average capacitance; placing at least one net at a desired location in an integrated circuit layout design, and estimating wire length of each net on the basis of the placement; comparing the estimated wire length of each net with the maximum wire length for that net; assigning first weights to nets whose estimated wire length value exceeds its maximum wire length value and assigning second weights, lower than the first weights, to nets whose estimated wire length value is less than its maximum wire length value; and, repeating the steps of placing, comparing and assigning until all nets have been placed in the integrated circuit layout design.
Claim 18
Dependent Claim
170 words
A computer implemented method for designing an integrated circuit layout comprising the computer implemented steps of: statistically determining a predictive interconnect capacitance for different types of integrated circuit layout nets; calculating an average capacitance per unit wire length for the integrated circuit layout; converting the predictive interconnect capacitance for each different type of net into a maximum wire length value using the calculated average capacitance; placing at least one net at a desired location in an integrated circuit layout design, and estimating wire length of each net on the basis of the placement; comparing the estimated wire length of each net with the maximum wire length for that net; assigning first weights to nets whose estimated wire length value exceeds its maximum wire length value and assigning second weights, lower than the first weights, to nets whose estimated wire length value is less than its maximum wire length value; and, repeating the steps of placing, comparing and assigning until all nets have been placed in the integrated circuit layout design.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-21 | 1998-05-23 | 1998-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-21 | 2002-05-23 | 2002-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-21 | 2006-05-23 | 2006-11-22 | $7700.00 | Window Closed / Lapsed |