Patent US6731173B1 successfully refreshed from Google Patents.
US5379232A
Expired / Lapsed
US
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Logic simulator
Assignee: Renesas Electronics Corp
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Filing: 1992-05-05
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Granted: 1995-01-03
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Expires: 2012-05-05
Abstract
Abstract There is disclosed a logic simulator having a wiring load extraction function which is capable of accurately calculating characteristic data of wiring loads when wirings are shortly spaced. A wiring region dividing unit (1) and a wiring load model generator (3) convert a wiring layout data (D10) into a wiring load model circuit data (D12) including wiring load models respectively for divided wiring regions into which a wiring is divided as a function of the number of adjacent wirings. A wiring load distributed constant calculator (4) extracts characteristic parameters in accordance with the number of adjacent wirings of each of the wiring load models in the circuit data (D12) from a unit length wiring characteristic parameter group (D13) including different characteristic parameters in accordance with the number of adjacent wirings, to output a distributed constant circuit data (D14) including the characteristic data of the respective wiring load models as a function of the characteristic parameters and the wiring lengths of the respective wiring load models. This enables the characteristic data of the wiring loads to be calculated with high accuracy.
Inventors
- 👤 Michio Komoda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:01
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
324 words
A logic simulator which functions to determine characteristic data of a wiring load of a logic circuit formed by a predetermined layout pattern, comprising: layout pattern data feed means for feeding a layout pattern data specifying the layout pattern of said logic circuit; wiring characteristic data storage means for storing characteristic parameters which are said characteristic data per unit length in corresponding relation to a plurality of types of wiring load models classified by a characteristic of a parasitic element incidental to a wiring; wiring load model setting means for setting said wiring load models specified by the characteristic of the parasitic element incidental to said wiring on said wiring between elements of said logic circuit as a function of said layout pattern data to output a wiring load model circuit data; and characteristic data calculation means receiving from said characteristic data storage means said characteristic parameters corresponding to said wiring load models of said wiring load model circuit data for calculating said characteristic data of said wiring load models as a function of said characteristic parameters and wiring lengths of said wiring load models to output a calculated characteristic data wiring load model circuit data; wherein said parasitic element incidental to said wiring is an inter-wiring parasitic element generated between said wiring and another adjacent wiring which is not directly connected to said wiring; and said wiring load model setting means includes: wiring region dividing means for dividing said wiring between the elements of said logic circuit into divided wiring regions in accordance with the characteristic of said inter-wiring parasitic element generated between said wiring and said adjacent wiring which is not directly connected to said wiring as a function of said layout pattern data; and wiring load model generation means for providing said wiring load models specified by the characteristic of said inter-wiring parasitic element respectively for said divided wiring regions of said wiring to output said wiring load model circuit data.
Claim 2
Dependent Claim
324 words
A logic simulator which functions to determine characteristic data of a wiring load of a logic circuit formed by a predetermined layout pattern, comprising: layout pattern data feed means for feeding a layout pattern data specifying the layout pattern of said logic circuit; wiring characteristic data storage means for storing characteristic parameters which are said characteristic data per unit length in corresponding relation to a plurality of types of wiring load models classified by a characteristic of a parasitic element incidental to a wiring; wiring load model setting means for setting said wiring load models specified by the characteristic of the parasitic element incidental to said wiring on said wiring between elements of said logic circuit as a function of said layout pattern data to output a wiring load model circuit data; and characteristic data calculation means receiving from said characteristic data storage means said characteristic parameters corresponding to said wiring load models of said wiring load model circuit data for calculating said characteristic data of said wiring load models as a function of said characteristic parameters and wiring lengths of said wiring load models to output a calculated characteristic data wiring load model circuit data; wherein said parasitic element incidental to said wiring is an inter-wiring parasitic element generated between said wiring and another adjacent wiring which is not directly connected to said wiring; and said wiring load model setting means includes: wiring region dividing means for dividing said wiring between the elements of said logic circuit into divided wiring regions in accordance with the characteristic of said inter-wiring parasitic element generated between said wiring and said adjacent wiring which is not directly connected to said wiring as a function of said layout pattern data; and wiring load model generation means for providing said wiring load models specified by the characteristic of said inter-wiring parasitic element respectively for said divided wiring regions of said wiring to output said wiring load model circuit data.
Claim 3
Dependent Claim
93 words
The logic simulator of claim 1, further comprising: wiring load model integration means receiving said wiring load model circuit data for producing a single integrated wiring load model from at least one of said wiring load models in said wiring load model circuit data to output an integrated wiring load model circuit data; and integrated wiring load model characteristic data calculation means for calculating said characteristic data of said integrated wiring load models in said integrated load model circuit data as a function of said calculated characteristic data wiring load model circuit data.
Claim 4
Dependent Claim
36 words
The logic simulator of claim 1, further comprising delay time calculation means for calculating a signal propagation delay time of said logic circuit as a function of said calculated characteristic data wiring load model circuit data.
Claim 5
Dependent Claim
19 words
The logic simulator of claim 1, wherein said characteristic data are distributed constants of a capacitance and a resistance.
Claim 6
Dependent Claim
53 words
The logic simulator of claim 1, wherein the characteristic of said inter-wiring parasitic element is classified by the number of adjacent wirings which are not directly connected to said wiring and by a degree of effect of a cross wiring which is not directly connected to said wiring and intersects said wiring two-dimensionally.
Claim 7
Dependent Claim
30 words
The logic simulator of claim 1, wherein the characteristic of said inter-wiring parasitic element is classifiied by the number of adjacent wirings which are not directly connected to said wiring.
Claim 8
Dependent Claim
36 words
The logic simulator of claim 6, wherein said wiring region dividing means divides said wiring in accordance with the number of adjacent wirings which are not directly connected to said wiring and at a branch point.
Claim 9
Dependent Claim
83 words
The logic simulator of claim 1, wherein said wiring load model setting means includes: wiring region dividing means for dividing said wiring between the elements of said logic circuit at predetermined intervals as a function of said layout pattern data to provide divided wiring regions; and wiring load model generation means for providing said wiring load models specified by the characteristic of said inter-wiring parasitic element respectively for said divided wiring regions of said wiring to output said wiring load model circuit data.
Claim 10
Dependent Claim
53 words
The logic simulator of claim 8, wherein the characteristic of said inter-wiring parasitic element is classified by the number of adjacent wirings which are not directly connected to said wiring and by a degree of effect of a cross wiring which is not directly connected to said wiring and intersects said wiring two-dimensionally.
Claim 11
Dependent Claim
93 words
The logic simulator of claim 8, further comprising: wiring load model integration means receiving said wiring load model circuit data for producing a single integrated wiring load model from at least one of said wiring load models in said wiring load model circuit data to output an integrated wiring load model circuit data; and integrated wiring load model characteristic data calculation means for calculating said characteristic data of said integrated wiring load models in said integrated load model circuit data as a function of said calculated characteristic data wiring load model circuit data.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-02 | 1998-07-04 | 1999-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-02 | 2002-07-04 | 2003-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-02 | 2006-07-04 | 2007-01-03 | $7700.00 | Window Closed / Lapsed |