Patent US6190165B1 successfully refreshed from Google Patents.
US5504037A
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Method of forming optimized thin film metal interconnects in integrated circuit structures of apparatus to reduce circuit operational delay
Assignee: Seiko Epson Corp
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Filing: 1993-07-29
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Granted: 1996-04-02
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Expires: 2013-07-29
Abstract
Abstract A method for forming optimized film metal interconnects employed in integrated circuit structures have a width, L, and a spatial separation or spacing, S, according to the following characteristics: interconnect width, L>/=0.1 mm; interconnect spatial separation, S>/=0.2 mu m, interconnect thickness, TA1</=2L mm; and interlayer insulating film thickness, TI</=2L min. More particularly, the layout is characterized by having the ranges of 0.1</=L</=0.8 mm and 0.2 mm</=S</=1 mm. As a result, IC signal switching speed is optimized for IC's designed in the sub-micron integration scale regime.
Inventors
- 👤 Seiichi Iwamatsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 23:49
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/495; Y; Y10; Y10S; Y10S428/00; Y10S428/901; Y10T; Y10T428/00; Y10T428/24; Y10T428/24802; Y10T428/24917
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
156 words
A method of forming an integrated circuit structure in the sub-micron integration scale regime, said method comprising: patterning thin film metal interconnects for the structure in a manner to optimize the overall reduction in spatial capacitance between interconnects by controlling the relationships between the width, L, spatial separation, S, and the thickness, T A1 , of the interconnects such that said interconnects have a width, L, in the range of 0.1 μm≦L≦1 μm, said interconnects have a spatial separation, S, in the range of 0.2 μm≦S≦1.0 μm, and the thickness, T A1 , of the interconnects is ≦2L; and forming an interlayer insulating film over the interconnects, said interlayer insulating film having a thickness T 1 in the range of 0.5 L μm≦T 1 ≦2L μm; whereby operational speed of the integrated circuit can be increased by controlling said relationships between L, S and T A1 to optimize overall reduction in interconnect spatial capacitance and resistance.
Claim 2
Independent Claim
156 words
A method of forming an integrated circuit structure in the sub-micron integration scale regime, said method comprising: patterning thin film metal interconnects for the structure in a manner to optimize the overall reduction in spatial capacitance between interconnects by controlling the relationships between the width, L, spatial separation, S, and the thickness, T A1 , of the interconnects such that said interconnects have a width, L, in the range of 0.1 μm≦L≦1 μm, said interconnects have a spatial separation, S, in the range of 0.2 μm≦S≦1.0 μm, and the thickness, T A1 , of the interconnects is ≦2L; and forming an interlayer insulating film over the interconnects, said interlayer insulating film having a thickness T 1 in the range of 0.5 L μm≦T 1 ≦2L μm; whereby operational speed of the integrated circuit can be increased by controlling said relationships between L, S and T A1 to optimize overall reduction in interconnect spatial capacitance and resistance.
Claim 3
Dependent Claim
18 words
The method of claim 1 wherein the interconnect width, L, is in the range of 0.1 μm≦L≦0.8S μm.
Claim 4
Dependent Claim
17 words
The method of claim 1 wherein the interconnect width, L, is the range of 0.1 μm≦L≦0.5S μm.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-02 | 1999-10-02 | 2000-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-02 | 2003-10-02 | 2004-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-02 | 2007-10-02 | 2008-04-02 | $7700.00 | Window Closed / Lapsed |