Semiconductor devices utilizing eutectic masks

Claim 1

A vertical power MOSFET semiconductor device which comprises (a) a substrate suitable for the manufacture of semiconductor devices, said substrate including at least a planar base of a semiconductor material and a planar layer of a dielectric and insulating material, said base having substantially parallel upper and lower major planar surfaces and a peripheral edge area interconnecting said major surfaces, said planar layer of a dielectric and insulating material being situated on and contiguous with defined portions of said upper major planar surface of said base designated as an array; (b) a thin film lamellar metallic eutectic on said defined portions of said planar layer of a dielectric and insulating material; (c) one of the phases of said thin film lamellar metallic eutectic forming said array of spaced metallic elements with substantially parallel spaces in-between said spaced metallic elements of said array; said elements of said array being less than one micron in width; (d) said parallel elements comprising an array of substantially parallel metallic gate contacts, the segments of said upper major surface of said base in-between said gate contacts being provided with: (e) first extended doped regions and second extended doped source regions, said extended doped regions underlying and extending between at least a portion of said gate contacts on either side of each said segment of said upper major surface of said base, each said second extended doped region being substantially bounded by said upper major surface of said base and by a first extended doped region; (f) source contacts at said source regions; and (g) at least one drain contact on said lower major planar surface of said body.