System and method for setting capacitive constraints on synthesized logic circuits

Claim 1

A method of synthesizing an integrated circuit, the steps of the method comprising: receiving and storing in a computer memory a netlist denoting a list of components in an integrated circuit and a set of nodes interconnecting said components; each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit; assigning a time delay value and a corresponding maximum capacitance value to each said node; computing a routing difficulty value, comprising a sum of routing difficulty values associated with each of said nodes in said integrated circuit; repeating the following steps until changes in said computed routing difficulty value meet predefined criteria: selecting one of said components; decreasing said time delay and maximum capacitance value associated with a node coupled to an output port of said component and increasing by corresponding amounts said time delay and maximum capacitance value associated with nodes coupled to input ports of said component; recomputing said routing difficulty value; and retaining said changed time delay and maximum capacitance values only if said recomputed routing difficulty value is smaller than its previous value; and passing said netlist and maximum capacitance values to a silicon compiler and automatically placing/routing an integrated circuit having said components and interconnection nodes with capacitance values not exceeding said maximum capacitance values; whereby said maximum capacitance values for said integrated circuit are automatically adjusted so as to reduce the difficulty of routing connections between said integrated circuit's components.

Claim 2

A method of synthesizing an integrated circuit, the steps of the method comprising: receiving and storing in a computer memory a netlist denoting a list of components in an integrated circuit and a set of nodes interconnecting said components; each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit; assigning a time delay value and a corresponding maximum capacitance value to each said node; computing a routing difficulty value, comprising a sum of routing difficulty values associated with each of said nodes in said integrated circuit; repeating the following steps until changes in said computed routing difficulty value meet predefined criteria: selecting one of said components; decreasing said time delay and maximum capacitance value associated with a node coupled to an output port of said component and increasing by corresponding amounts said time delay and maximum capacitance value associated with nodes coupled to input ports of said component; recomputing said routing difficulty value; and retaining said changed time delay and maximum capacitance values only if said recomputed routing difficulty value is smaller than its previous value; and passing said netlist and maximum capacitance values to a silicon compiler and automatically placing/routing an integrated circuit having said components and interconnection nodes with capacitance values not exceeding said maximum capacitance values; whereby said maximum capacitance values for said integrated circuit are automatically adjusted so as to reduce the difficulty of routing connections between said integrated circuit's components.

Claim 9

A method of synthesizing an integrated circuit, the steps of the method comprising: receiving and storing in a computer memory a netlist which specifies an integrated circuit by denoting a list of components in said integrated circuit and a set of nodes interconnecting said components; each said component of said integrated circuit having at least one input port and at least one output port; assigning a time delay value and a corresponding initial maximum capacitance value to each said node, wherein said assigned values are consistent with a predefined set of timing constraints on said integrated circuit's operation; computing a routing difficulty value for said integrated circuit, said routing difficulty value comprising a predefined function of the said maximum capacitance values for said nodes; for each of at least of a plurality of components in said integrated circuit: decreasing said maximum capacitance value for at least one of said component's output nodes and increasing by a corresponding amount said maximum capacitance value for at least one node coupled to an input port of said component; said changes in said maximum capacitance values being retained only when said changes decrease said computed routing difficulty value; and passing said netlist and maximum capacitance values to a silicon compiler for automatically placing/routing an integrated circuit having said components and interconnection nodes with capacitance values not exceeding said maximum capacitance values.

Claim 10

A method of synthesizing an integrated circuit, the steps of the method comprising: receiving and storing in a computer memory a netlist which specifies an integrated circuit by denoting a list of components in said integrated circuit and a set of nodes interconnecting said components; each said component of said integrated circuit having at least one input port and at least one output port; assigning a time delay value and a corresponding initial maximum capacitance value to each said node, wherein said assigned values are consistent with a predefined set of timing constraints on said integrated circuit's operation; computing a routing difficulty value for said integrated circuit, said routing difficulty value comprising a predefined function of the said maximum capacitance values for said nodes; for each of at least of a plurality of components in said integrated circuit: decreasing said maximum capacitance value for at least one of said component's output nodes and increasing by a corresponding amount said maximum capacitance value for at least one node coupled to an input port of said component; said changes in said maximum capacitance values being retained only when said changes decrease said computed routing difficulty value; and passing said netlist and maximum capacitance values to a silicon compiler for automatically placing/routing an integrated circuit having said components and interconnection nodes with capacitance values not exceeding said maximum capacitance values.

Claim 11

A method of synthesizing an integrated circuit, the steps of the method comprising: receiving and storing in a computer memory a netlist which specifies an integrated circuit by denoting a list of components in said integrated circuit and a set of nodes interconnecting said components; each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit; each said node being coupled to a number of said components; providing a set of timing constraints for propagation of signals from specified ones of said circuit input nodes to specified ones of said circuit output nodes; defining a set of signal delays associated with said components denoted in said netlist; assigning a time delay value and a corresponding initial maximum capacitance value to each said node, wherein said assigned values are consistent with said set of timing constraints; computing a routing difficulty value, comprising a sum of routing difficulty values associated with all of said nodes in said integrated circuit, each said routing difficulty value comprising a predefined function of the said maximum capacitance value for a corresponding node and said number of integrated circuit components coupled to said node; repeating the following steps until changes in said computed routing difficulty value meet predefined criteria: for each component in said integrated circuit, beginning with components coupled to said output nodes and progressing toward components adjacent said input nodes: decreasing said time delay associated with a node coupled to an output port of said component by decreasing said maximum capacitance value for at least one of said component's output nodes and increasing by a corresponding amount said maximum capacitance value for at least one node coupled to an input port of said component; said changes in said maximum capacitance values being retained only when said changes decrease said computed routing difficulty value; and passing said netlist and maximum capacitance values to a silicon compiler for automatically placing/routing an integrated circuit having said components and interconnection nodes with capacitance values not exceeding said maximum capacitance values.

Claim 12

A method of synthesizing an integrated circuit, the steps of the method comprising: receiving and storing in a computer memory a netlist which specifies an integrated circuit by denoting a list of components in said integrated circuit and a set of nodes interconnecting said components; each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit; each said node being coupled to a number of said components; providing a set of timing constraints for propagation of signals from specified ones of said circuit input nodes to specified ones of said circuit output nodes; defining a set of signal delays associated with said components denoted in said netlist; assigning a time delay value and a corresponding initial maximum capacitance value to each said node, wherein said assigned values are consistent with said set of timing constraints; computing a routing difficulty value, comprising a sum of routing difficulty values associated with all of said nodes in said integrated circuit, each said routing difficulty value comprising a predefined function of the said maximum capacitance value for a corresponding node and said number of integrated circuit components coupled to said node; repeating the following steps until changes in said computed routing difficulty value meet predefined criteria: for each component in said integrated circuit, beginning with components coupled to said output nodes and progressing toward components adjacent said input nodes: decreasing said time delay associated with a node coupled to an output port of said component by decreasing said maximum capacitance value for at least one of said component's output nodes and increasing by a corresponding amount said maximum capacitance value for at least one node coupled to an input port of said component; said changes in said maximum capacitance values being retained only when said changes decrease said computed routing difficulty value; and passing said netlist and maximum capacitance values to a silicon compiler for automatically placing/routing an integrated circuit having said components and interconnection nodes with capacitance values not exceeding said maximum capacitance values.