Non-volatile memory device

Claim 2

A memory device comprising first and second terminal regions, first and second barrier means disposed between the terminal regions, and a conductive region between the first and second barrier means, the dimensional extent of the barrier means and the conductive region being configured to be sufficiently small that the device exhibits first and second relatively high and relatively low stable resistive states in the absence of a voltage applied between the terminal regions.

Claim 3

A memory device according to claim 1 including switching means for switching the device between said first and second states.

Claim 4

A memory device according to claim 2 wherein the switching means comprises means for applying a switching voltage to the terminal regions.

Claim 5

A memory device according to claim 1 which exhibits said relatively high and low resistive states at room temperature.

Claim 6

A memory device according to claim 4 wherein at room temperature, the ratio between the values of the first and second states exceeds 250:1.

Claim 7

A memory device according to claim 4 wherein at room temperature, the ratio between the values of the first and second states lies between 5:1 and 500:1.

Claim 8

A device according to claim 1 including a substrate formed with overlying layers which provide the first and second barrier means and the conductive region, and which have been formed into a plurality of pillars at least some of which are of a diameter for exhibiting said relatively high and low conductivity states in the absence of a voltage applied between the terminal regions.

Claim 9

A device according to claim 7 wherein a plurality of the pillars have diameters within a range of 20 to 50 nm.

Claim 10

A device according to claim 7 wherein the first and second barrier means comprise AlAs/GaAs heterojunctions.

Claim 11

A device according to claim 9 wherein the conductive region between the barrier means comprises an i-GaAs layer.

Claim 12

A device according to claim 7, wherein the terminal regions include respective layers of n-GaAs material.

Claim 13

A device according to claim 7, including a conductive overlayer bridging the first terminal regions of the individual pillars.

Claim 14

A device according to claim 12 wherein the overlayer comprises a vapour deposited metallic layer.

Claim 15

A non-volatile memory device comprising an array of memory cells, each of the cells comprising: first and second terminal regions, first and second barrier means disposed between the terminal regions, and a conductive region between the first and second barrier means, the dimensional extent of the barrier means and the conductive regions being configured to be sufficiently small that the cell exhibits first and second stable resistive states in the absence of a voltage applied between the terminal regions said first stable resistive state exhibiting a relatively high resistance and said second resistive state exhibiting a relatively low resistance; writing means for writing data in the memory cells individually by switching the cells between said first and second stable resistive states; and reading means for reading data from the cells individually in response to the first and second stable resistive states thereof.

Claim 16

A non-volatile memory device comprising an array of memory cells, each of the cells comprising: first and second terminal regions, first and second barrier means disposed between the terminal regions, and a conductive region between the first and second barrier means, the dimensional extent of the barrier means and the conductive regions being configured to be sufficiently small that the cell exhibits first and second stable resistive states in the absence of a voltage applied between the terminal regions said first stable resistive state exhibiting a relatively high resistance and said second resistive state exhibiting a relatively low resistance; writing means for writing data in the memory cells individually by switching the cells between said first and second stable resistive states; and reading means for reading data from the cells individually in response to the first and second stable resistive states thereof.

Claim 17

A non-volatile memory device according to claim 14 wherein the cells are arranged in rows and columns, and the writing means comprises row and column lines for applying respective voltages which in a preselected combination switch an individually addressed one of the cells between the first and second stable resistive states thereof.

Claim 18

A non-volatile memory device according to claim 15 wherein the reading means comprises a plurality of row and column lines for applying a reading voltage to the cells individually for reading the first and second stable resistive states thereof.

Claim 19

A memory device according to claim 14 including a plurality of row and column lines associated with the cells, switching means associated with the row and column lines for selecting the cells individually.

Claim 20

A memory device according to claim 14 wherein the cells are formed on a common substrate with overlying layers which provide the first and second barrier means and the conductive region, wherein for each cell the substrate and said overlying layers have been formed into a plurality of pillars at least some of which are of a diameter for exhibiting said relatively high and low conductivity states in the absence of a voltage applied between the terminal regions.

Claim 21

A device according to claim 8 wherein the first and second barrier means comprise AlAs/GaAs heterojunctions.

Claim 22

A device according to claim 19 wherein the conductive region between the barrier means comprises an i-GaAs layer.