Data processor with an integer multiplication function on a fractional multiplier

Claim 2

A data processor, comprising: a controller for receiving one of a first instruction and a second instruction, the controller decoding the first instruction to provide a first control signal and a second control signal, the controller decoding the second instruction to provide a third control signal and a fourth control signal; a data bus for providing a plurality of data values; an accumulator having an input coupled to the data bus for receiving a first one of the plurality of data values; first shifting means coupled to the accumulator for receiving the first one of the plurality of data values, the first shifting means selectively right shifting the first one of the plurality of data values by fifteen bits in response to the first control signal, the first shifting means selectively transferring the first one of the plurality of data values without shifting in response to the third control signal; a first register having an input coupled to the data bus for receiving a second one of the plurality of data values; a second register having an input coupled to the data bus for receiving a third one of the plurality of data values; a multiplier for selectively multiplying the second one of the plurality of data values and the third one of the plurality of data values to provide a product; an adder having a first input coupled to the first shifting means for receiving a transferred output and a second input coupled to the multiplier for receiving the product, the adder selectively adding the transferred output and the product to provide a sum; and second shifting means coupled to the adder for receiving the sum, the second shifting means selectively left shifting the sum by fifteen bits and transferring a shifted sum to the accumulator in response to the second control signal, the second shifting means selectively transferring the sum without shifting in response to the fourth control signal.

Claim 3

The data processor of claim 1 wherein the first instruction is an integer multiply accumulate instruction having a mnemonic form of IMAC.

Claim 4

The data processor of claim 1 wherein the second instruction is a fractional multiply accumulate instruction having a mnemonic form of MAC.

Claim 5

The data processor of claim 1 wherein the first control signal is asserted when an integer multiply accumulate instruction is executed, the second control signal is asserted when an integer instruction is executed, the third control signal is asserted when a fractional multiply accumulate instruction is executed, and the fourth control signal is asserted when a fractional instruction is executed.

Claim 6

The data processor of claim 1 wherein the controller decodes one of the first instruction and the second instruction to provide a fifth control signal, the fifth control signal enabling the multiplier to multiply the second and third ones of the plurality of data values to provide the product.

Claim 7

The data processor of claim 1 wherein the controller decodes one of the first instruction and the second instruction to provide a sixth control signal, the sixth control signal enabling the adder to add the transferred output and the product to provide the sum.

Claim 8

The data processor of claim 1 wherein the controller receives a third instruction and decodes the third instruction to provide a fifth control signal to the first shifting means, the first shifting means outputting a value of zero in response to the fifth control signal.

Claim 9

The data processor of claim 1 wherein the first shifting means comprises a plurality of shift cells, wherein each of the plurality of shift cells corresponds to a bit of the first one of the plurality of data values.

Claim 10

The data processor of claim 8 wherein each of the plurality of bit cells shifts a more significant bit of the first one of the plurality of data values when the first control signal is asserted and a corresponding bit of the first one of the plurality of data values when the third control signal is asserted.

Claim 11

The data processor of claim 9 wherein each of the plurality of bits cells shifts a zero when a fifth control signal is asserted.

Claim 12

The data processor of claim 1 wherein the second shifting means comprises a plurality of shift cells, wherein each of the plurality of shift cells corresponds to a bit of the sum.

Claim 13

The data processor of claim 11 wherein each of the plurality of bit cells shifts a less significant bit of the sum when the second control signal is asserted and a corresponding bit of the sum when the fourth control signal is asserted.

Claim 16

The method of claim 13 wherein the first instruction is an integer multiply accumulate instruction and the second instruction is a fractional multiply accumulate instruction.

Claim 17

The method of claim 13 further comprising the steps of: asserting the first control signal when the first instruction is an integer multiply accumulate instruction; asserting the second control signal when the first instruction is an integer instruction; asserting the third control signal when the second instruction is a multiply accumulate instruction; and asserting the fourth control signal when the second instruction is a fractional instruction.

Claim 18

A data processor, comprising: a controller for receiving one of an integer multiplication accumulation instruction and a fractional multiplication accumulation instruction, the controller decoding the integer multiplication instruction to provide a first control signal and a second control signal, the controller decoding the fractional multiplication instruction to provide a third control signal and a fourth control signal; a data bus for providing a plurality of data values; an accumulator having an input coupled to the data bus for receiving a first one of the plurality of data values; first shifting means coupled to the accumulator for receiving the first one of the plurality of data values, the first shifting means selectively right shifting the first one of the plurality of data values by fifteen bits in response to the first control signal, the first shifting means selectively transferring the first one of the plurality of data values without right shifting in response to the third control signal; a first register having an input coupled to the data bus for receiving a second one of the plurality of data values; a second register having an input coupled to the data bus for receiving a third one of the plurality of data values; a multiplier for selectively multiplying the second one of the plurality of data values and the third one of the plurality of data values to provide a product; an adder having a first input coupled to the first shifting means for receiving a transferred output and a second input coupled to the multiplier for receiving the product, the adder selectively adding the transferred output and the product to provide a sum; and second shifting means coupled to the adder for receiving the sum, the second shifting means selectively left shifting the sum by fifteen bits and transferring a shifted sum to the accumulator in response to the second control signal, the second shifting means selectively transferring the sum without shifting in response to the fourth control signal.

Claim 19

A data processor, comprising: a controller for receiving one of an integer multiplication accumulation instruction and a fractional multiplication accumulation instruction, the controller decoding the integer multiplication instruction to provide a first control signal and a second control signal, the controller decoding the fractional multiplication instruction to provide a third control signal and a fourth control signal; a data bus for providing a plurality of data values; an accumulator having an input coupled to the data bus for receiving a first one of the plurality of data values; first shifting means coupled to the accumulator for receiving the first one of the plurality of data values, the first shifting means selectively right shifting the first one of the plurality of data values by fifteen bits in response to the first control signal, the first shifting means selectively transferring the first one of the plurality of data values without right shifting in response to the third control signal; a first register having an input coupled to the data bus for receiving a second one of the plurality of data values; a second register having an input coupled to the data bus for receiving a third one of the plurality of data values; a multiplier for selectively multiplying the second one of the plurality of data values and the third one of the plurality of data values to provide a product; an adder having a first input coupled to the first shifting means for receiving a transferred output and a second input coupled to the multiplier for receiving the product, the adder selectively adding the transferred output and the product to provide a sum; and second shifting means coupled to the adder for receiving the sum, the second shifting means selectively left shifting the sum by fifteen bits and transferring a shifted sum to the accumulator in response to the second control signal, the second shifting means selectively transferring the sum without shifting in response to the fourth control signal.

Claim 20

The data processor of claim 16 wherein the controller receives a third instruction to provide a fifth control signal to the first shifting means, the first shifting means outputting a value of zero in response to the fifth control signal.

Claim 21

The data processor of claim 17 where the first shift means comprises a plurality of shift cells wherein each of the plurality of shift cells corresponds to a bit of the sum, each of the plurality of shift cells shifts a more significant bit of the sum when the first control signal is asserted, a corresponding bit of the sum when the third control signal is asserted, and a zero when the fifth control signal is asserted.

Claim 22

The data processor of claim 16 wherein the second shifting means comprises a plurality of shift cells wherein each of the shift cells corresponds to bit of the sum, each of the plurality of shift cells shifts a less significant bit of the sum when the second control signal is asserted and a corresponding bit of the sum when the fourth control signal is asserted.