US5438539A
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Memory device, method for reading information from the memory device, method for writing information into the memory device, and method for producing the memory device
Assignee: NEW ENRGY AND INDUSTRIAL TECHNICAL DEVELOPMENT ORGANIZATION
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Filing: 1994-09-02
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Granted: 1995-08-01
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Expires: 2014-09-02
Abstract
Abstract A memory device includes a first address signal line, a pair of second address signal lines, a standby signal line, and a memory cell provided at a cross point at which the first address signal line crosses the pair of second address signal lines. The memory cell includes first and second elements connected, via a connection node, in series between the pair of second address signal lines in a forward direction, each of the first and second elements having a negative-differential conductance characteristic. A threshold diode is connected between the first address signal line and the connection node, and has a characteristic in which a current flows in the threshold diode when a voltage applied across the threshold diode exceeds threshold voltages. A gate is connected to the standby signal line and controls currents flowing in the first and second elements.
Inventors
- 👤 Toshihiko Mori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:38
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/36; G11C11/56; H; H10; H10B; H10B10/00; G11C2211/00; G11C2211/56; G11C2211/561; G11C2211/5614
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
154 words
A memory device comprising: a first address signal line; a pair of second address signal lines; a standby signal line; and a memory cell provided at a cross point at which the first address signal line crosses the pair of second address signal lines, said memory cell comprising: first and second elements connected, via a connection node, in series between the pair of second address signal lines and in a forward direction, each of the first and second elements having a negative-differential conductance characteristic, a threshold diode connected between the first address signal line and the connection node, the threshold diode having a characteristic in accordance with which a current flows in the threshold diode when a voltage applied across the threshold diode exceeds one of a positive and a negative threshold voltages, and a gate which is connected to the standby signal line and controls currents flowing in the first and second elements.
Claim 2
Dependent Claim
154 words
A memory device comprising: a first address signal line; a pair of second address signal lines; a standby signal line; and a memory cell provided at a cross point at which the first address signal line crosses the pair of second address signal lines, said memory cell comprising: first and second elements connected, via a connection node, in series between the pair of second address signal lines and in a forward direction, each of the first and second elements having a negative-differential conductance characteristic, a threshold diode connected between the first address signal line and the connection node, the threshold diode having a characteristic in accordance with which a current flows in the threshold diode when a voltage applied across the threshold diode exceeds one of a positive and a negative threshold voltages, and a gate which is connected to the standby signal line and controls currents flowing in the first and second elements.
Claim 3
Dependent Claim
53 words
The memory device as claimed in claim 1, wherein: the current flows in the threshold diode when a voltage equal to or higher than the positive threshold voltage is applied across the threshold diode and when a voltage equal to or lower than the negative threshold voltage is applied across the threshold diode.
Claim 4
Dependent Claim
138 words
The memory device as claimed in claim 1, wherein: the first address signal line comprises a first layer; the threshold diode has a first portion connected to the first layer, and a second portion; the first element has a first portion connected to the second portion of the threshold diode, and a second portion; the second element has a first portion connected to the second portion of the threshold diode, and a second portion; the second portion of the first element is located above and connected to one of the pair of second address signal lines; the second portion of the second element is located above and connected to the other one of the pair of second address signal lines; and the gate includes a gate electrode located above resonant-tunneling barrier layers of the first and second elements.
Claim 5
Dependent Claim
56 words
The memory device as claimed in claim 1, wherein the memory device is maintained in one of a first stable operating point, located at a valley portion of a current-voltage characteristic curve of the first element, and a second stable operating point, located at a valley portion of a current-voltage characteristic curve of the second element.
Claim 6
Dependent Claim
20 words
The memory device as claimed in claim 1, wherein one of the pair of second address signal lines is grounded.
Claim 7
Dependent Claim
78 words
The memory device as claimed in claim 1, further comprising means for setting the standby signal line to a first potential, thereby causing currents flowing in the first and second elements to be increased when information is read from or written into the memory cell and for setting the standby signal line to a second potential, thereby causing the currents flowing in the first and second elements to be decreased when information is held in the memory cell.
Claim 8
Independent Claim
285 words
A method for reading information from a memory device comprising a first address signal line, a pair of second address signal lines, a standby signal line and a memory cell provided at a cross point at which the first address signal line crosses the pair of second address signal lines, said memory cell comprising first and second elements connected, via a connection node, in a series circuit between the pair of second address signal lines in a forward direction, each of the first and second elements having a negative-differential conductance characteristic, a threshold diode connected between the first address signal line and the connection node, the threshold diode having a characteristic in which a current flows when a voltage applied across the threshold diode exceeds one of a positive threshold voltage and a negative threshold voltage, and a gate which is connected to the standby signal line and controls currents flowing in the first and second elements, said method comprising the steps of: applying voltages to the pair of second address signal lines so that two stable operating points and an unstable operating point are formed by the series circuit of the first and second elements in accordance with the voltages applied to the pair of second address signal lines; and applying a Voltage to the first address signal line such that a potential of the connection model corresponding to one of the stable operating points, with respect to the first address signal line is outside a voltage range between the negative threshold voltage and the positive threshold voltage and a potential of the connection node corresponding to the unstable operating point with respect to the first address signal line is within said voltage range.
Claim 9
Independent Claim
285 words
A method for reading information from a memory device comprising a first address signal line, a pair of second address signal lines, a standby signal line and a memory cell provided at a cross point at which the first address signal line crosses the pair of second address signal lines, said memory cell comprising first and second elements connected, via a connection node, in a series circuit between the pair of second address signal lines in a forward direction, each of the first and second elements having a negative-differential conductance characteristic, a threshold diode connected between the first address signal line and the connection node, the threshold diode having a characteristic in which a current flows when a voltage applied across the threshold diode exceeds one of a positive threshold voltage and a negative threshold voltage, and a gate which is connected to the standby signal line and controls currents flowing in the first and second elements, said method comprising the steps of: applying voltages to the pair of second address signal lines so that two stable operating points and an unstable operating point are formed by the series circuit of the first and second elements in accordance with the voltages applied to the pair of second address signal lines; and applying a Voltage to the first address signal line such that a potential of the connection model corresponding to one of the stable operating points, with respect to the first address signal line is outside a voltage range between the negative threshold voltage and the positive threshold voltage and a potential of the connection node corresponding to the unstable operating point with respect to the first address signal line is within said voltage range.
Claim 10
Dependent Claim
31 words
The method as claimed in claim 7, further comprising the step of applying a voltage to the gate so that the currents flowing in the first and second elements are increased.
Claim 11
Dependent Claim
276 words
The method as claimed in claim 7, further comprising: (a) applying the voltages to the first address signal line and the pair of second address signal lines so that the potential of the connection node, corresponding to one of the two stable operating points, on a negative-potential side with respect to the first address signal line is lower than the negative threshold voltage and the potential of the connection node, corresponding to the unstable operating point, with respect to the first address signal line is higher than the negative threshold voltage when information corresponding to said one of the two stable operating points on the negative-potential side is read from the memory cell; (b) applying the voltages to the first address signal line and the pair of second address signal lines so that the potential of the connection node, corresponding to one of the stable operating points, on a positive-potential side with respect to the first address signal line is higher than the negative threshold voltage and the potential of the connection node corresponding to the unstable operating point, with respect to the first address signal line is lower than the negative threshold voltage when information corresponding to said one of the two stable operating points on the positive-potential side is read from the memory cell; (c) applying a first voltage to the standby signal line so that currents flowing in the first and second elements are increased in the steps (a) and (b); and (d) applying a second voltage to the standby signal line so that the currents flowing in the first and second elements are decreased when information is held in the memory cell.
Claim 12
Dependent Claim
119 words
The method as claimed in claim 9, wherein: said step (a) comprises the steps of applying a high-level signal to the first address signal line, and applying a low-level signal lower than the high-level signal to one of the pair of second address signal lines; said step (b) comprises the steps of applying a low-level signal to said one of the pair of second address signal lines and applying a high-level signal to the other one of the pair of second address signal lines; said step (c) comprises the step of setting the standby signal line at a zero or positive potential; and said step (d) comprises the step of setting the standby signal line at a negative potential.
Claim 13
Dependent Claim
112 words
The method as claimed in claim 9, wherein: said step (a) comprises the steps of applying a high-level signal to the first address signal line, and applying a low-level signal lower than the high-level signal to both of the pair of second address signal lines; said step (b) comprises the steps of applying a low-level signal to one of the pair of second address signal lines, and applying a high-level signal to the first address signal line; said step (c) comprises the step of setting the standby signal line at a zero or positive potential; and said step (d) comprises the step of setting the standby signal line at a negative potential.
Claim 14
Independent Claim
199 words
A method for writing information into a memory device comprising first and second elements connected, via a connection node, in a series circuit between a pair of second address signal lines in a forward direction, each of the first and second elements having a negative-differential conductance characteristic, a threshold diode connected between the first address signal line and the connection node, the threshold diode having a characteristic in which a current flows when a voltage applied across the threshold diode exceeds one of a positive threshold voltage and a negative threshold voltage and a gate which is connected to the standby signal line and controls currents flowing in the first and second elements, said method comprising the steps of: applying voltages to the pair of second address signal lines so that two stable operating points and an unstable operating point are formed by the series circuit of the first and second elements; and applying a voltage to the first address signal line so that a potential of the connection node, corresponding to the unstable operating point, with respect to the first address signal line is outside a voltage range between the negative threshold voltage and the positive threshold voltage.
Claim 15
Independent Claim
199 words
A method for writing information into a memory device comprising first and second elements connected, via a connection node, in a series circuit between a pair of second address signal lines in a forward direction, each of the first and second elements having a negative-differential conductance characteristic, a threshold diode connected between the first address signal line and the connection node, the threshold diode having a characteristic in which a current flows when a voltage applied across the threshold diode exceeds one of a positive threshold voltage and a negative threshold voltage and a gate which is connected to the standby signal line and controls currents flowing in the first and second elements, said method comprising the steps of: applying voltages to the pair of second address signal lines so that two stable operating points and an unstable operating point are formed by the series circuit of the first and second elements; and applying a voltage to the first address signal line so that a potential of the connection node, corresponding to the unstable operating point, with respect to the first address signal line is outside a voltage range between the negative threshold voltage and the positive threshold voltage.
Claim 16
Dependent Claim
31 words
The method as claimed in claim 12, further comprising the step of applying a voltage to the gate so that the currents flowing in the first and second elements are increased.
Claim 17
Dependent Claim
186 words
The method as claimed in claim 12, wherein said step comprises: (a) applying the voltages to the first address signal line and the pair of second address signal lines so that the potential of the connection node, corresponding to the unstable operating point, with respect to the first address signal line is higher than the positive threshold voltage when information corresponding to said one of the two stable operating points on the negative-potential side is written into the memory cell; (b) applying the voltages to the first address signal line and the pair of second address signal lines so that the potential of the connection node, corresponding to the unstable operating point with respect to the first address signal line is lower than the negative threshold voltage when information corresponding to said one of the two stable operating points on the positive-potential side is written into the memory cell; and (c) applying a voltage to the standby signal line so that currents flowing in the first and second elements are increased in the steps (a) and (b) and when information is held in the: memory cell.
Claim 18
Dependent Claim
114 words
The method as claimed in claim 12, wherein: said step (a) comprises the steps of applying a low-level signal to the first address signal line and applying a high-level signal, lower than the high-level signal, to one of the pair of second address signal lines; said step (b) comprises the steps of applying a high-level signal to the first address signal line and applying a low-level signal to the other one of the pair of second address signal lines; said step (c) comprises the step of setting the standby signal line at a zero or positive potential; and said step (d) comprises the step of setting the standby signal line at a negative potential.
Claim 19
Dependent Claim
255 words
A semiconductor device comprising: a plurality of first address signal lines; a plurality of pairs of second address signal lines; a plurality of standby signal lines extending in parallel with the plurality of pairs of second address signal lines; a plurality of memory cells provided at cross points at which the plurality of first address signal lines and the plurality of pairs of second address signal line cross; first address decoder means for supplying first address signals to the plurality of first address signal lines; second address decoder means for supplying second address signals to the plurality of pairs of second address signal lines and for supplying standby signals to the plurality of standby signal lines; and sense amplifier means for sensing information read from the memory cells to the plurality of first address signal lines, each of the memory cells comprising: first and second elements connected, via a connection node, in series between one of the pairs of second address signal lines in a forward direction, each of the first and second elements having a negative-differential conductance characteristic; a threshold diode connected between one of the first address signal lines and the connection node, the threshold diode having a characteristic in accordance with which a current flows in the threshold diode when a voltage applied across the threshold diode exceeds one of a negative threshold voltage and a positive threshold voltage; and a gate which is connected to one of the standby signal lines and controls currents flowing in the first and second elements.
Claim 20
Dependent Claim
255 words
A semiconductor device comprising: a plurality of first address signal lines; a plurality of pairs of second address signal lines; a plurality of standby signal lines extending in parallel with the plurality of pairs of second address signal lines; a plurality of memory cells provided at cross points at which the plurality of first address signal lines and the plurality of pairs of second address signal line cross; first address decoder means for supplying first address signals to the plurality of first address signal lines; second address decoder means for supplying second address signals to the plurality of pairs of second address signal lines and for supplying standby signals to the plurality of standby signal lines; and sense amplifier means for sensing information read from the memory cells to the plurality of first address signal lines, each of the memory cells comprising: first and second elements connected, via a connection node, in series between one of the pairs of second address signal lines in a forward direction, each of the first and second elements having a negative-differential conductance characteristic; a threshold diode connected between one of the first address signal lines and the connection node, the threshold diode having a characteristic in accordance with which a current flows in the threshold diode when a voltage applied across the threshold diode exceeds one of a negative threshold voltage and a positive threshold voltage; and a gate which is connected to one of the standby signal lines and controls currents flowing in the first and second elements.
Claim 21
Dependent Claim
23 words
The memory device as claimed in claim 16, wherein each of the pairs of second address signal lines is integrally formed and grounded.
Claim 22
Dependent Claim
109 words
The memory device as claimed in claim 16, wherein the second decoder means further comprises means for setting one of the standby signal lines at a first potential and thereby causing currents, flowing in the first and second elements of one of the memory cells, to be increased when information is read from or written into said one of the memory cells and for setting said one of the standby signal lines at a second potential and thereby causing the currents, flowing in the first and second elements of said one of the memory cells, to be decreased when information is held in said one of the memory cells.
Claim 23
Independent Claim
135 words
A method of producing a memory device, comprising the steps of: (a) forming a first address signal line layer; (b) forming a layer structure of a threshold diode on the first address signal line layer, said layer structure of the threshold diode having a single-barrier layer; (c) forming a layer structure of a first element and a layer structure of a second element on the layer structure of the threshold diode, each of the first and second elements having a negative-differentiation characteristic, and the layer structure of each of the first and second elements including a double-barrier layer and a gate electrode located at a level higher than that of the double-barrier layer; and (d) forming a pair of second address signal line layers on the respective layer structures of the first and second elements.
Claim 24
Independent Claim
135 words
A method of producing a memory device, comprising the steps of: (a) forming a first address signal line layer; (b) forming a layer structure of a threshold diode on the first address signal line layer, said layer structure of the threshold diode having a single-barrier layer; (c) forming a layer structure of a first element and a layer structure of a second element on the layer structure of the threshold diode, each of the first and second elements having a negative-differentiation characteristic, and the layer structure of each of the first and second elements including a double-barrier layer and a gate electrode located at a level higher than that of the double-barrier layer; and (d) forming a pair of second address signal line layers on the respective layer structures of the first and second elements.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-07-31 | 1999-01-30 | 1999-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-31 | 2003-01-30 | 2003-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-31 | 2007-01-30 | 2007-08-01 | $7700.00 | Window Closed / Lapsed |