Method of making a universal quantum dot logic cell

Claim 1

A method of fabricating a quantum-effect logic unit, comprising the steps of: providing a semiconductor substrate; forming a first barrier layer on said substrate; forming a quantum layer on said first barrier layer; forming a second barrier layer on said quantum layer; etching a plurality of spaced-apart trenches through said second barrier layer and said quantum layer to said first barrier layer to define quantum dots between said trenches; regrowing a semiconductor in said trenches having a wider band gap than said quantum layer to form a respective plurality of vertical heterojunction barriers; forming a tunneling inhibitor comprising a gap between one of said quantum dots and said quantum layer external to said trenches; forming a plurality of gate bodies adjacent said quantum dots to be operable to apply potentials to said quantum dots; and forming source and drain contacts laterally to the regrown semiconductor to be electrically coupled to said quantum layer external to said trenches.

Claim 2

A method of fabricating a quantum-effect logic unit, comprising the steps of: providing a semiconductor substrate; forming a first barrier layer on said substrate; forming a quantum layer on said first barrier layer; forming a second barrier layer on said quantum layer; etching a plurality of spaced-apart trenches through said second barrier layer and said quantum layer to said first barrier layer to define quantum dots between said trenches; regrowing a semiconductor in said trenches having a wider band gap than said quantum layer to form a respective plurality of vertical heterojunction barriers; forming a tunneling inhibitor comprising a gap between one of said quantum dots and said quantum layer external to said trenches; forming a plurality of gate bodies adjacent said quantum dots to be operable to apply potentials to said quantum dots; and forming source and drain contacts laterally to the regrown semiconductor to be electrically coupled to said quantum layer external to said trenches.

Claim 3

A method of fabricating a quantum-effect logic cell, comprising the steps of: providing a semiconductor substrate; forming a first barrier layer on said substrate; forming a quantum layer on said first barrier layer; forming a second barrier layer on said quantum layer; etching a plurality of spaced-apart separator trenches through said second barrier layer and said quantum layer to said first barrier layer to define a plurality of parallel quantum dot rows between said separator trenches; etching a plurality of spaced-apart trenches through said second barrier layer and said quantum layer to said first barrier layer to define quantum dots between said trenches; regrowing a semiconductor in said trenches having a wider band gap than said quantum layer to form a respective plurality of vertical heterojunction barriers; forming a tunneling inhibitor between a quantum dot of said first row of quantum dots and said quantum layer external to said trenches; forming a plurality of parallel coupled gate bodies adjacent said quantum dots to be operable to apply potentials to said quantum dots; and forming source and drain contacts laterally to the regrown semiconductor to be electrically coupled to said quantum layer external to said trenches.

Claim 4

A method of fabricating a quantum-effect logic cell, comprising the steps of: providing a semiconductor substrate; forming a first barrier layer on said substrate; forming a quantum layer on said first barrier layer; forming a second barrier layer on said quantum layer; etching a plurality of spaced-apart separator trenches through said second barrier layer and said quantum layer to said first barrier layer to define a plurality of parallel quantum dot rows between said separator trenches; etching a plurality of spaced-apart trenches through said second barrier layer and said quantum layer to said first barrier layer to define quantum dots between said trenches; regrowing a semiconductor in said trenches having a wider band gap than said quantum layer to form a respective plurality of vertical heterojunction barriers; forming a tunneling inhibitor between a quantum dot of said first row of quantum dots and said quantum layer external to said trenches; forming a plurality of parallel coupled gate bodies adjacent said quantum dots to be operable to apply potentials to said quantum dots; and forming source and drain contacts laterally to the regrown semiconductor to be electrically coupled to said quantum layer external to said trenches.